Vertical transistor fabrication for memory applications

Patent metadata

Field	Value
Publication number	US-2021028282-A1
Application number	US-201916519246-A
Country	US
Kind code	A1
Filing date	Jul 23, 2019
Priority date	Jul 23, 2019
Publication date	Jan 28, 2021
Grant date	—

Abstract

The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

First claim

1 . A memory cell device, comprising:
a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate; and a channel structure formed in the film stack, the channel structure comprising:
a channel layer comprising a semiconductor material, the channel layer having a gradient dopant concentration and a gradual change in thickness along a vertical stacking of the film stack;
a first dielectric layer disposed along a sidewall of the channel layer, the first dielectric layer comprising an oxide;
a second dielectric layer disposed along a sidewall of the first dielectric layer, the second dielectric layer comprising a nitride; and
a protective blocking layer formed on the substrate and disposed between the film stack and the second dielectric layer, the protective blocking layer comprising an oxide, wherein the protective blocking layer has a gradual change in thickness along a vertical stacking of the film stack.

2 . (canceled)

3 . The memory cell device of claim 1 , wherein the protective blocking layer has a first thickness at a bottom portion of the protective blocking layer greater than a second thickness at a top portion of the protective blocking layer.

4 . The memory cell device of claim 3 , wherein the first thickness is between about 5% and about 80% greater than the second thickness.

5 . The memory cell device of claim 1 , wherein the channel layer has a first dopant concentration at a bottom portion of the channel layer greater than a second dopant concentration at a top portion of the channel layer.

6 . The memory cell device of claim 5 , wherein the first dopant concentration is between about 200% and about 400% greater than the second dopant concentration.

7 . The memory cell device of claim 1 , wherein the channel layer is a doped silicon containing layer, group III-V material, IGZO or gallium oxide material.

8 . The memory cell device of claim 1 , wherein the protective blocking layer is a dielectric layer.

9 . The memory cell device of claim 1 , wherein the channel layer is a doped polysilicon layer and the protective blocking layer is at least one of SiO 2 , SiON, SiCON, or SiOC.

10 . (canceled)

11 . A memory cell device, comprising:
a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate; and a channel structure formed in the film stack, the channel structure comprising:
a channel layer having a gradient dopant concentration and a gradual change in thickness along a vertical stacking of the film stack;
a dielectric layer disposed along a sidewall of the channel layer; and
a protective blocking layer formed on the substrate and disposed between the film stack and the dielectric layer, wherein the protective blocking layer has a gradual change in thickness along a vertical stacking of the film stack.

12 . The memory cell device of claim 11 , wherein the protective blocking layer has a first thickness at a bottom portion of the protective blocking layer greater than a second thickness at a top portion of the protective blocking layer.

13 . (canceled)

14 . The memory cell device of claim 11 , wherein the channel layer has a first dopant concentration at a bottom portion of the channel layer greater than a second dopant concentration at a top portion of the channel layer.

15 . The memory cell device of claim 11 , wherein the channel layer is a doped polysilicon layer and the protective blocking layer is at least one of SiO 2 , SiON, SiCON, SiN, SiC or SiOC.

16 - 20 . (canceled)

21 . The memory cell device of claim 1 , wherein the protective blocking layer has a first thickness at a bottom portion of the protective blocking layer less than a second thickness at a top portion of the protective blocking layer.

22 . The memory cell device of claim 21 , wherein the first thickness is between about 5% and about 80% less than the second thickness.

23 . The memory cell device of claim 1 , wherein the channel layer has a first dopant concentration at a bottom portion of the channel layer less than a second dopant concentration at a top portion of the channel layer.

24 . The memory cell device of claim 23 , wherein the first dopant concentration is between about 200% and about 400% less than the second dopant concentration.

25 . The memory cell device of claim 11 , wherein the protective blocking layer has a first thickness at a bottom portion of the protective blocking layer less than a second thickness at a top portion of the protective blocking layer.

26 . The memory cell device of claim 14 , wherein the first dopant concentration is between about 200% and about 400% greater than the second dopant concentration.

27 . The memory cell device of claim 11 , wherein the channel layer has a first dopant concentration at a bottom portion of the channel layer less than a second dopant concentration at a top portion of the channel layer.

28 . The memory cell device of claim 27 , wherein the first dopant concentration is between about 200% and about 400% less than the second dopant concentration.

Assignees

• Applied Materials Inc

Inventors

• Kumar Arvind
• Manhas Sanjeev
• Pakala Mahendra
• Yieh Ellie Y

Classifications

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/40

  Crystalline structures · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D62/314 Primary

  having vertical doping variations  (vertical IGFETs H10D30/63) · CPC title