Methods of manufacturing a fan-out panel level semiconductor package

Patent metadata

Field	Value
Publication number	US-12315822-B2
Application number	US-202418403583-A
Country	US
Kind code	B2
Filing date	Jan 3, 2024
Priority date	Jun 25, 2020
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
preparing a frame structure comprising a core portion and a plurality of lower pads under the core portion, wherein a cavity penetrates the core portion;
attaching an adhesive film to each of the plurality of lower pads of the frame structure;
mounting a semiconductor chip in the cavity of the frame structure, wherein the semiconductor chip comprises an active surface on which a plurality of bump pads are arranged and a non-active surface opposite the active surface;
forming a molding member to cover the frame structure and the semiconductor chip;
attaching a carrier substrate to the molding member;
performing a planarization process on a first surface that is exposed by removing the adhesive film, wherein each of the plurality of bump pads of the semiconductor chip has a polygonal column shape or cylindrical shape;
forming a redistribution structure on the first surface that is planarized;
forming an opening portion in the molding member through a second surface that is exposed by removing the carrier substrate; and
attaching an external connection terminal to the redistribution structure.

2. The method of claim 1 , wherein the molding member surrounds all surfaces of the semiconductor chip.

3. The method of claim 1 , wherein the planarization process is performed to allow a lower surface of the lower pad, lower surfaces of the plurality of bump pads, and a lower surface of the molding member to be coplanar.

4. The method of claim 3 , wherein a lower surface of the core portion and the active surface are spaced apart from the redistribution structure by a distance.

5. The method of claim 3 , wherein, through the planarization process, the lower surfaces of the plurality of bump pads have planarized surfaces.

6. The method of claim 5 , wherein, through the planarization process, a surface-roughness of the lower surface of the lower pad is substantially equal to a surface roughness of the lower surfaces of the plurality of bump pads.

7. The method of claim 1 , wherein the frame structure further comprises:
a plurality of upper pads on the core portion; and
a plurality of through vias that connect the plurality of upper pads and the plurality of lower pads, wherein the plurality of through vias have an hourglass shape with a concave middle portion.

8. The method of claim 1 , wherein the molding member fills between the plurality of lower pads and between the plurality of bump pads, and
the molding member is in contact with an upper surface of the redistribution structure.

9. The method of claim 1 , wherein the plurality of bump pads have a thickness of about 5 μm to about 20 μm from the active surface to an upper surface of the redistribution structure.

10. The method of claim 1 , wherein the redistribution structure comprises a redistribution line and a redistribution via connected to the redistribution line, wherein the redistribution via has a tapered shape that increases in width as a distance from the semiconductor chip increases.

11. A method of manufacturing a semiconductor package, the method comprising:
forming a first sub-package comprising a first semiconductor chip;
forming a second sub-package comprising a second semiconductor chip; and
stacking the second sub-package on the first sub-package using a connection structure,
wherein the forming of the first sub-package comprises:
preparing a frame structure comprising a core portion and a plurality of lower pads under the core portion, wherein a cavity penetrates the core portion;
attaching an adhesive film to each of the plurality of lower pads of the frame structure;
mounting the first semiconductor chip in the cavity of the frame structure, wherein the first semiconductor chip comprises an active surface on which a plurality of bump pads are arranged and a non-active surface opposite the active surface;
forming a molding member to cover the frame structure and the first semiconductor chip;
attaching a carrier substrate to the molding member;
performing a planarization process on a first surface that is exposed by removing the adhesive film, wherein each of the plurality of bump pads of the first semiconductor chip has a polygonal column shape or a cylindrical shape;
forming a redistribution structure on the first surface that is planarized; and
forming an opening portion in the molding member through a second surface that is exposed by removing the carrier substrate.

12. The method of claim 11 , wherein the frame structure comprises:
an upper pad on the core portion; and
a through via connecting the upper pad to the lower pad, and
the connection structure is formed in the opening portion and connected to the upper pad.

13. The method of claim 11 , wherein the molding member surrounds all surfaces of the first semiconductor chip, a lower surface of the frame structure, an upper surface of the redistribution structure, a side surface of the lower pad, and side surfaces of the plurality of bump pads.

14. The method of claim 11 , wherein, through the planarization process, a surface roughness of a lower surface of the lower pad is substantially equal to a surface roughness of lower surfaces of the plurality of bump pads.

15. The method of claim 11 , wherein the first semiconductor chip and the second semiconductor chip are of different types.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeongho
• Lee Doohwan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title