Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Patent metadata

Field	Value
Publication number	US-9865525-B2
Application number	US-201414326789-A
Country	US
Kind code	B2
Filing date	Jul 9, 2014
Priority date	Mar 23, 2012
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a plurality of modular interconnect units by providing a core material and forming a plurality of vertical interconnect structures extending through the core material to a surface of the modular interconnect units;
disposing the modular interconnect units and semiconductor die in proximity to each other;
depositing an encapsulant over and around the semiconductor die and modular interconnect units;
removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion of the encapsulant over the surface of the modular interconnect units; and
forming an opening through the second portion of the encapsulant extending to the vertical interconnect structures of the modular interconnect units.

2. The method of claim 1 , further including forming an interconnect structure over the semiconductor die and modular interconnect units.

3. The method of claim 1 , further including forming an insulating layer over the surface of the semiconductor die and modular interconnect units.

4. The method of claim 1 , wherein providing the modular interconnect units further includes:
forming a first insulating layer over a first surface of the core material; and
forming a second insulating layer over a second surface of the core material opposite the first surface of the core material.

5. The method of claim 1 , wherein the modular interconnect units include a cross-shape, angled or L-shape, circular shape, or oval shape.

6. The method of claim 1 , wherein a height of the modular interconnect units is less than a height of the semiconductor die.

7. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a plurality of modular interconnect units by,
(a) providing a core material,
(b) forming a plurality of conductive interconnect structures extending through the core material to a surface of the modular interconnect units, and
(c) forming a first insulating layer over a first surface of the core material;

disposing the modular interconnect units around the semiconductor die;
depositing an encapsulant over and around the semiconductor die and modular interconnect units;
removing a first portion of the encapsulant while leaving a second portion of the encapsulant over the surface of the modular interconnect units; and
forming an opening through the second portion of the encapsulant extending to the conductive interconnect structures of the modular interconnect units.

8. The method of claim 7 , wherein providing the modular interconnect units further includes forming a second insulating layer over a second surface of the core material opposite the first surface of the core material.

9. The method of claim 7 , wherein the conductive interconnect structures each include a metal cap and a protection layer formed over the metal cap.

10. The method of claim 7 , further including
removing the first portion of the encapsulant extending to a surface of the semiconductor die.

11. The method of claim 7 , further including forming an interconnect structure over the semiconductor die and modular interconnect units.

12. The method of claim 7 , wherein the modular interconnect units include a cross-shape, angled or L-shape, circular shape, or oval shape.

13. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a plurality of modular interconnect units by providing a core material and forming a plurality of conductive interconnect structures extending through the core material to a surface of the modular interconnect units;
disposing a plurality of modular interconnect units around the semiconductor die, wherein a height of the modular interconnect units is less than a height of the semiconductor die;
depositing an encapsulant over and around the semiconductor die and modular interconnect units; and
forming an opening through the encapsulant over the modular interconnect units extending to the conductive interconnect structures of the modular interconnect units.

14. The method of claim 13 , further including forming an internal filler material within the conductive interconnect structures.

15. The method of claim 14 , wherein the internal filler material includes an insulating material.

16. The method of claim 13 , further including:
forming a first insulating layer over a first surface of the core material; and
forming a second insulating layer over a second surface of the core material opposite the first surface of the core material.

17. The method of claim 13 , wherein the conductive interconnect structures each include a metal cap and a protection layer formed over the metal cap.

18. The method of claim 13 , wherein forming the opening in the encapsulant includes:
removing a first portion of the encapsulant while leaving a second portion of the encapsulant over the surface of the modular interconnect units; and
removing part of the second portion of the encapsulant extending to the conductive interconnect structures of the modular interconnect units.

19. The method of claim 13 , wherein the modular interconnect units include a cross-shape, angled or L-shape, circular shape, or oval shape.

20. A semiconductor device, comprising:
a semiconductor die;
a modular interconnect unit disposed around the semiconductor die, wherein the modular interconnect unit includes a core material and a plurality of vertical interconnect structures extending through the core material and a height of the modular interconnect unit is less than a height of the semiconductor die; and
an encapsulant deposited around the semiconductor die and modular interconnect unit with an opening through the encapsulant over the modular interconnect unit extending to the vertical interconnect structures of the modular interconnect unit.

21. The semiconductor device of claim 20 , further including an internal filler material formed within the vertical interconnect structures.

22. The semiconductor device of claim 21 , wherein the internal filler material includes an insulating material.

23. The semiconductor device of claim 20 , further including:
a first insulating layer formed over a first surface of the core material; and
a second insulating layer formed over a second surface of the core material opposite the first surface of the core material.

24. The semiconductor device of claim 20 , further including an interconnect structure formed over the semiconductor die and modular interconnect unit.

25. The semiconductor device of claim 20 , wherein the modular interconnect unit includes a cross-shape, angled or L-shape, circular shape, or oval shape.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Marimuthu Pandi C
• Chen Kang
• GU Yu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title