Electronic package and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10410970-B1
Application number	US-201815993108-A
Country	US
Kind code	B1
Filing date	May 30, 2018
Priority date	Mar 6, 2018
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

An electronic package is provided. An electronic component and a plurality of conductive pillars are provided on a carrier structure. An encapsulation layer encapsulates the electronic component and the conductive pillars. Each of the conductive pillars has a peripheral surface narrower than two end surfaces of the conductive pillar. Therefore, the encapsulation layer is better bonded to the conductive pillars. A method for fabricating the electronic package is also provided.

First claim

What is claimed is:

1. An electronic package, comprising:
a carrier structure;
at least one electronic component provided on and electrically connected with the carrier structure;
a plurality of conductive pillars provided on the carrier structure via a plurality of conductors of solder material, wherein the conductive pillars each include two opposite end faces and a peripheral surface adjoining the two end faces and being narrower than the two end faces, and the peripheral surface is curved inwards with respect to the two end faces such that the peripheral surface forms a concave arc; and
at least one encapsulation layer encapsulating the electronic component and the conductive pillars, wherein the encapsulation layer includes a first surface and a second surface, the first surface is combined with the carrier structure, and the two end faces of the conductive pillars are free from protruding from the second surface of the encapsulation layer.

2. The electronic package of claim 1 , wherein the conductive pillars are electrically connected with the carrier structure.

3. The electronic package of claim 1 , wherein the carrier structure includes a first side and a second side opposite to the first side, with a plurality of electronic components provided on at least one of the first side and the second side.

4. The electronic package of claim 1 , wherein the carrier structure includes a first side and a second side opposite to the first side, with a plurality of encapsulation layers provided on at least one of the first side and the second side.

5. The electronic package of claim 1 , wherein a portion of a surface of the electronic component is exposed from a surface of the encapsulation layer.

6. The electronic package of claim 1 , further comprising a bonding pad embedded in the encapsulation layer at a location corresponding to a location of the electronic component and at least partially exposed from a surface of the encapsulation layer.

7. The electronic package of claim 1 , further comprising a shielding element shielding the electronic component.

8. The electronic package of claim 1 , further comprising a wiring structure provided on the encapsulation layer and electrically connected with at least one of the conductive pillars and the electronic component.

9. A method for fabricating an electronic package, comprising:
providing a conductive frame including a plate and a plurality of conductive pillars connected with the plate, wherein the conductive pillars each include two opposite end faces and a peripheral surface adjoining the two end faces and being narrower than the two end faces, and the peripheral surface is curved inwards with respect to the two end faces such that the peripheral surface forms a concave arc;
bonding onto a carrier structure at least one electronic component and the conductive frame via the conductive pillars;
encapsulating the electronic component and the conductive pillars with at least one encapsulation layer; and
removing an entirety of the plate of the conductive frame.

10. The method of claim 9 , further comprising electrically connecting the conductive pillars with the carrier structure.

11. The method of claim 9 , further comprising bonding the conductive pillars onto the carrier structure via a plurality of conductors.

12. The method of claim 9 , wherein the conductive frame is formed by removing a portion of a metal plate to form recesses separating the conductive pillars.

13. The method of claim 9 , wherein the carrier structure includes a first side and a second side opposite to the first side, with a plurality of electronic components provided on the first side and the second side.

14. The method of claim 9 , wherein the carrier structure includes a first side and a second side opposite to the first side, with a plurality of encapsulation layers provided on the first side and the second side.

15. The method of claim 9 , wherein a portion of a surface of the electronic component is exposed from a surface of the encapsulation layer.

16. The method of claim 9 , wherein the conductive frame further includes a bonding pad disposed at a location corresponding to a location of the electronic component and at least partially exposed from the encapsulation layer.

17. The method of claim 9 , further comprising forming a shielding element shielding the electronic component.

18. The method of claim 9 , further comprising, after removing the plate, forming on the encapsulation layer a wiring structure electrically connected with the conductive pillars.

19. The method of claim 9 , further comprising, after removing the plate, forming on the encapsulation layer a wiring structure electrically connected with the electronic component.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chiu Chih-Hsien
• Chen Chia-Yang

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title