Method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-12310043-B2
Application number	US-202117498645-A
Country	US
Kind code	B2
Filing date	Oct 11, 2021
Priority date	Dec 15, 2016
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a gate electrode structure over a first region of a semiconductor substrate, wherein the gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and first and second gate sidewalls;
forming a source/drain region on a second region of the semiconductor substrate, wherein the second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer;
forming an interlayer dielectric layer over the source/drain region and the first and second gate sidewalls; and
forming an oxide layer over the interlayer dielectric layer, source/drain region, and uppermost surfaces of the first and second gate sidewalls without substantially forming the oxide layer on the metal gate electrode layer,
wherein a first outermost edge of the oxide layer is flush with a first outermost edge of the first gate sidewall and a second outermost edge of the oxide layer is flush with a second outermost edge of the second gate sidewall when viewed in cross section.

2. The method according to claim 1 , wherein the metal gate electrode layer includes a plurality of metal layers.

3. The method according to claim 1 , wherein the interlayer dielectric layer is made of one or more layers of silicon oxide, silicon nitride, or a combination thereof.

4. The method according to claim 1 , wherein the oxide layer is silicon dioxide.

5. The method according to claim 4 , wherein the oxide layer is formed by a reaction of a silicon halide and oxygen.

6. The method according to claim 4 , wherein the oxide layer has a height of about 5 nm to about 20 nm.

7. A method for fabricating a semiconductor device, comprising:
forming a fin structure over a semiconductor substrate, wherein the fin structure extends in a first direction;
forming a gate electrode structure over the fin structure, wherein the gate electrode structure extends in a second direction substantially perpendicular to the first direction, and the gate electrode structure includes first and second gate sidewalls;
forming a source/drain region in the fin structure on opposing sides of the gate electrode structure;
forming an oxide layer over uppermost surfaces of the first and second gate sidewalls and over the source/drain region without substantially forming the oxide layer over the gate electrode structure, wherein a first outermost edge of the oxide layer is flush with a first outermost edge of the first gate sidewall and a second outermost edge of the oxide layer is flush with a second outermost edge of the second gate sidewall when viewed in cross section;
forming an insulating layer over the gate electrode structure;
forming an interlayer dielectric layer over the insulating layer and the oxide layer;
forming a via in the interlayer dielectric layer and the oxide layer exposing the source/drain region; and
depositing a conductive material in the via to form a source/drain contact.

8. The method according to claim 7 , wherein the gate electrode structure includes a metal gate electrode layer.

9. The method according to claim 8 , wherein the metal gate electrode layer is formed by chemical vapor deposition, atomic layer deposition, or electroplating.

10. The method according to claim 7 , wherein the insulating layer includes one or more layers formed by SiN, SiCN, or SiOCN.

11. The method according to claim 7 , wherein the interlayer dielectric layer is formed by chemical vapor deposition.

12. The method according to claim 7 , wherein the source/drain contact is formed of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, nickel, and alloys thereof.

13. The method according to claim 7 , wherein a contact barrier liner layer is formed in the via prior to forming the source/drain contact.

14. A method for fabricating a semiconductor device, comprising:
forming a fin structure over a semiconductor substrate, wherein the fin structure extends in a first direction;
forming a gate electrode structure over a first region of the fin structure, wherein the gate electrode structure includes a metal gate electrode layer, the gate electrode structure extends in a second direction substantially perpendicular to the first direction, and first and second sidewalls of the gate electrode structure are surrounded by a first interlayer dielectric layer;
recessing the metal gate electrode layer to form a recessed metal gate electrode layer;
forming an oxide layer over the first interlayer dielectric layer and over uppermost surfaces of the first and second sidewalls of the gate electrode structure by reacting a halide compound with oxygen, wherein a first outermost edge of the oxide layer is flush with a first outermost edge of the first sidewall and a second outermost edge of the oxide layer is flush with a second outermost edge of the second sidewall when viewed in cross section; and
forming a second interlayer dielectric layer over the oxide layer.

15. The method according to claim 14 , wherein the metal gate electrode layer is recessed by a metal gate etch back operation.

16. The method according to claim 14 , wherein the halide compound is silicon halide.

17. The method according to claim 14 , wherein the oxide layer is silicon dioxide.

18. The method according to claim 14 , wherein the oxide layer has a height of about 5 nm to about 20 nm.

19. The method according to claim 14 , wherein the second interlayer dielectric layer is formed by chemical vapor deposition.

20. The method according to claim 14 , wherein the first and second interlayer dielectric layers are made of one or more layers of silicon oxide, silicon nitride, or a combination thereof.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen
• Lin Li-Te
• Huang Yu-Lien

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title