Method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-10164067-B2
Application number	US-201715644600-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Dec 15, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a dummy gate electrode structure over a region of a semiconductor substrate;
forming an insulating layer over the dummy gate electrode structure;
removing the dummy gate electrode structure;
forming a gate electrode structure over the region of the semiconductor substrate where the dummy gate electrode structure was removed; and
forming an oxide layer overlying the insulating layer by reacting a halide compound with oxygen to increase a height of the insulating layer without substantially forming an oxide layer over the gate electrode structure.

2. The method according to claim 1 , wherein the halide compound is silicon tetrachloride.

3. The method according to claim 1 , wherein the oxide layer is silicon dioxide.

4. The method according to claim 1 , wherein a height of the oxide layer overlying the insulating layer is about 5 nm to about 20 nm.

5. The method according to claim 1 , wherein the gate electrode structure comprises a high k gate dielectric layer and a metal gate electrode formed over the high k gate dielectric layer.

6. The method according to claim 5 , further comprising performing an etch back of the metal gate electrode before forming the oxide layer on the insulating layer.

7. A method for fabricating a semiconductor device, comprising:
forming a dummy gate electrode structure over a region of a semiconductor substrate;
forming a first insulating layer over the dummy gate electrode structure;
removing the dummy gate electrode structure;
forming a gate electrode structure over the region of the semiconductor substrate where the dummy gate electrode structure was removed;
forming a second insulating layer over the gate electrode structure;
forming an oxide layer overlying the first insulating layer by reacting a halide compound with oxygen to increase a height of the insulating layer without substantially forming an oxide layer over the second insulating layer;
forming a via in the first insulating layer and second insulating layer exposing the gate electrode structure; and
depositing a conductive material in the via to form a gate electrode contact.

8. The method according to claim 7 , wherein the halide compound is silicon tetrachloride.

9. The method according to claim 7 , wherein the oxide layer is silicon dioxide.

10. The method according to claim 7 , wherein the gate electrode structure comprises a high k gate dielectric layer and a metal gate electrode formed over the high k gate dielectric layer.

11. The method according to claim 10 , further comprising recessing the metal gate electrode before forming the second insulating layer on the gate electrode structure.

12. The method according to claim 7 , wherein the second insulating layer is a nitride layer.

13. A method for fabricating a semiconductor device, comprising:
forming a dummy gate electrode structure over a first region of a semiconductor substrate;
forming a first interlayer dielectric layer around the dummy gate electrode structure;
removing the dummy gate electrode structure;
forming a gate electrode structure over the first region of the semiconductor substrate where the dummy gate electrode structure was removed,
wherein the gate electrode structure includes a high-k dielectric layer and a metal gate electrode layer disposed over the high-k dielectric layer;
recessing the metal gate electrode layer to form a recessed metal gate electrode layer;
forming a cap insulating layer over the recessed metal gate electrode layer;
recessing the cap insulating layer; and
forming an oxide layer overlying the first interlayer dielectric layer by reacting a halide compound with oxygen to increase a height of the first interlayer dielectric layer without substantially forming an oxide layer over the cap insulating layer.

14. The method according claim 13 , further comprising forming a second interlayer dielectric layer over the first interlayer dielectric layer and the cap insulating layer.

15. The method according to claim 14 , further comprising:
forming a first via in the second interlayer dielectric layer and the cap insulating layer exposing the metal gate electrode layer; and
depositing a first conductive material in the first via to form a gate electrode contact.

16. The method according to claim 15 , further comprising forming source/drain regions over second regions of the semiconductor substrate on opposing sides of the first region of the semiconductor substrate.

17. The method according to claim 16 , further comprising:
forming second vias in the second interlayer dielectric layer, the oxide layer, and the first interlayer dielectric layer exposing the source/drain regions; and
depositing a second conductive material in the second vias to form source/drain region contacts.

18. The method according to claim 13 , wherein the halide compound is silicon tetrachloride.

19. The method according to claim 13 , wherein the oxide layer is silicon dioxide.

20. The method according to claim 13 , wherein the cap insulating layer is a nitride layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen
• Lin Li-Te
• Huang Yu-Lien

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title