Hdp fill with reduced void formation and spacer damage

Patent metadata

Field	Value
Publication number	US-2016379873-A1
Application number	US-201514750741-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

First claim

1 . A method for filling gaps between structures in a semiconductor device, comprising:
forming a plurality of high aspect ratio structures adjacent to one another to provide gaps therebetween; forming a first dielectric layer on tops of the high aspect ratio structures; conformally depositing a spacer dielectric layer over the high aspect ratio structures; removing the spacer dielectric layer from horizontal surfaces; conformally depositing a protection layer over the high aspect ratio structures; filling the gaps with a flowable dielectric; recessing the flowable dielectric to a height along sidewalls of the high aspect ratio structures by a selective etch process such that the protection layer protects the spacer dielectric layer on the sidewalls of the high aspect ratio structures; exposing the first dielectric layer and the spacer dielectric layer by an etch process that selectively removes the protection layer above the height wherein the first dielectric layer and the spacer dielectric layer have a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the recessing step and the exposing step; and filling the gaps by a high density plasma fill.

2 . The method as recited in claim 1 , wherein conformally depositing a spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a material having a higher etch resistance than SiN.

3 . The method as recited in claim 2 , wherein the spacer dielectric layer includes SiBCN.

4 . The method as recited in claim 1 , wherein forming a first dielectric layer includes forming the first dielectric layer with a material having a higher etch resistance than SiN.

5 . The method as recited in claim 4 , wherein the first dielectric layer includes SiBCN.

6 . The method as recited in claim 1 , wherein conformally depositing a spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a thickness of 12 nm or less to increase a gap size between high aspect ratio structures without altering a pitch between the high aspect ratio structures.

7 . The method as recited in claim 6 , wherein filling the gaps by a high density plasma fill includes avoiding formation of voids by providing the gap size.

8 . The method as recited in claim 1 , further comprising forming contact holes by etching through the flowable dielectric and the protection layer.

9 - 20 . (canceled)

21 . The method as recited in claim 1 , wherein conformally depositing the spacer dielectric layer includes conformally depositing the spacer dielectric layer along the sidewalls of the high aspect ratio structures.

22 . The method as recited in claim 1 , wherein conformally depositing the protection layer includes conformally depositing the protection layer in the gaps.

23 . The method as recited in claim 1 , wherein exposing the first dielectric layer and the spacer dielectric layer includes forming horns on top corners of each of the plurality of high aspect ratio structures.

24 . The method as recited in claim 1 , wherein exposing the first dielectric layer and the spacer dielectric layer includes selectively removing the protection layer such that a portion of the protection layer remains above the height of the flowable dielectric.

25 . The method as recited in claim 1 , wherein exposing the first dielectric layer includes exposing a top surface of the first dielectric layer.

26 . The method as recited in claim 1 , further comprising:
removing the first dielectric layer and a gate material between the spacer dielectric layer; and forming a replacement metal gate between the spacer dielectric layer, wherein the replacement metal gate includes a high-k dielectric layer and a metal fill layer.

27 . The method as recited in claim 8 , further comprising forming contacts within the contact holes, wherein the contacts include a contact liner and a metal contact.

28 . The method as recited in claim 1 , wherein the plurality of high aspect ratio structures includes a height to width ratio greater than 1:1.

29 . The method as recited in claim 1 , wherein the plurality of high aspect ratio structures includes a height to width ratio greater than 3:1.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Bu Huiming
• Greene Andrew M
• Pranatharthiharan Balasubramanian
• Xie Ruilong

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title