Method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-11145749-B2
Application number	US-201816229979-A
Country	US
Kind code	B2
Filing date	Dec 21, 2018
Priority date	Dec 15, 2016
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a gate electrode structure over a first region of a semiconductor substrate;
wherein the forming the gate electrode structure comprises:
forming a sacrificial gate dielectric layer overlying the substrate;
forming a sacrificial gate electrode layer overlying the sacrificial gate dielectric layer;
forming a hard mask layer overlying the sacrificial gate electrode layer;
patterning the hard mask layer to form a patterned hard mask;
removing portions of the sacrificial gate electrode layer and sacrificial gate dielectric layer not covered by the patterned hard mask; and
removing the patterned hard mask;

selectively forming a first oxide layer overlying the sacrificial gate electrode layer by reacting a halide compound with oxygen to increase a height of the sacrificial gate electrode layer;
forming source/drain regions on second regions of the semiconductor substrate, wherein the second regions of the semiconductor substrate are on opposing sides of the sacrificial gate electrode layer;
forming an interlayer dielectric layer over the gate electrode structure and the source/drain regions;
removing the first oxide layer, the interlayer dielectric layer over the first oxide layer, the sacrificial gate dielectric layer, and the sacrificial gate electrode layer to create a gate space;
forming a gate dielectric layer in the gate space;
forming a gate electrode layer over the gate dielectric layer in the gate space; and
forming a second oxide layer over a remaining portion of the interlayer dielectric layer surrounding the gate electrode layer without substantially forming the second oxide layer on the gate electrode layer.

2. The method according to claim 1 , wherein the halide compound is silicon tetrachloride.

3. The method according to claim 1 , wherein the first oxide layer is silicon dioxide.

4. The method according to claim 1 , wherein a height of the first oxide layer overlying the sacrificial gate electrode structure is about 5 nm to about 20 nm.

5. The method according to claim 1 , further comprising before forming the gate electrode structure:
patterning the substrate to form a fin extending in a first direction; and
forming the gate electrode structure overlying the fin and extending in a second direction substantially perpendicular to the first direction.

6. The method according to claim 1 , wherein the sacrificial gate electrode layer is formed by at least one method selected from the CVD, ALD, and electroplating.

7. The method according to claim 1 , wherein the sacrificial gate dielectric layer includes one or more layers of a dielectric material.

8. The method according to claim 1 , wherein the gate electrode layer includes a plurality of metal layers.

9. A method for fabricating a semiconductor device, comprising:
forming a fin structure over a semiconductor substrate, wherein the fin structure extends in a first direction;
forming a gate electrode structure over the fin structure, wherein the gate electrode structure extends in a second direction substantially perpendicular to the first direction, and sidewalls of the gate electrode structure are surrounded by a first insulating layer;
forming a second insulating layer over the gate electrode structure;
forming an oxide layer overlying the first insulating layer by reacting a halide compound with oxygen to increase a height of the first insulating layer without substantially forming an oxide layer over the second insulating layer;
forming a first via in the second insulating layer exposing the gate electrode structure; and
depositing a conductive material in the first via to form a gate electrode contact.

10. The method according to claim 9 , further comprising:
forming a second via in the oxide layer and first insulating layer exposing a source/drain structure; and
depositing a conductive material in the second via to form a source/drain contact.

11. The method according to claim 9 , wherein the halide compound is silicon tetrachloride.

12. The method according to claim 9 , wherein the oxide layer is silicon dioxide.

13. The method according to claim 9 , further comprising recessing the metal gate electrode before forming the second insulating layer on the gate electrode structure.

14. The method according to claim 9 , wherein the second insulating layer is a nitride layer.

15. A method for fabricating a semiconductor device, comprising:
forming a fin structure over semiconductor substrate, wherein the fin structure extend in a first direction;
forming a gate electrode structure over a first region of the fin structure, wherein the gate electrode structure extends in a second direction substantially perpendicular to the first direction, and sidewalls of the gate electrode structure are surrounded by a first interlayer dielectric layer;
recessing the metal gate electrode layer to form a recessed metal gate electrode layer;
forming an insulating layer over the recessed metal gate electrode layer;
recessing the insulating layer; and
forming an oxide layer overlying the first interlayer dielectric layer by reacting a halide compound with oxygen to increase a height of the first interlayer dielectric layer without substantially forming an oxide layer over the insulating layer.

16. The method according claim 15 , further comprising forming a second interlayer dielectric layer over the first interlayer dielectric layer and the insulating layer.

17. The method according to claim 16 , further comprising:
forming a first via in the second interlayer dielectric layer and the insulating layer exposing the metal gate electrode layer; and
depositing a first conductive material in the first via to form a gate electrode contact.

18. The method according to claim 15 , further comprising forming source/drain regions over a second region of the fin structure on opposing sides of the first region of the fin structure.

19. The method according to claim 18 , further comprising:
forming second vias in the second interlayer dielectric layer, the oxide layer, and the first interlayer dielectric layer exposing the source/drain regions; and
depositing a second conductive material in the second vias to form source/drain region contacts.

20. The method according to claim 15 , wherein the insulating layer is a nitride layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen
• Huang Yu-Lien
• Lin Li-Te

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title