Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor device and method for fabricating the same
US2016284641A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016284641-A1 |
| Application number | US-201514692762-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 22, 2015 |
| Priority date | Mar 26, 2015 |
| Publication date | Sep 29, 2016 |
| Grant date | — |
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- Title
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Abstract
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A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.
First claim
Opening claim text (preview).
1 - 7 . (canceled) 8 . A semiconductor device, comprising: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask comprises silicon nitride. 9 . The semiconductor device of claim 8 , wherein the gate structure comprises a gate electrode and a spacer adjacent to the gate electrode, the semiconductor device further comprises: the first hard mask on the gate electrode; and the second hard mask on the first hard mask. 10 . (canceled) 11 . The semiconductor device of claim 8 , wherein the gate structure comprises a gate electrode and a spacer adjacent to the gate electrode, the semiconductor device further comprises: the first hard mask on the gate electrode and the spacer; and the second hard mask on the first hard mask. 12 . (canceled) 13 . The semiconductor device of claim 8 , wherein the gate structure comprises a gate electrode and a spacer adjacent to the gate electrode, the semiconductor device further comprises: the first hard mask on the gate electrode; and the second hard mask on the gate electrode and directly contacting the gate electrode. 14 . The semiconductor device of claim 8 , wherein the gate structure comprises a gate electrode and a spacer adjacent to the gate electrode, the semiconductor device further comprises: the first hard mask on the spacer; and the second hard mask on the gate electrode and directly contacting the gate electrode. 15 . The semiconductor device of claim 8 , wherein the first hard mask comprises silicon nitride and the second hard mask comprises silicon oxide. 16 . The semiconductor device of claim 8 , further comprising: a second ILD layer on the first ILD layer, the first hard mask, and the second hard mask; and a contact plug passing through the second ILD layer and the second hard mask and directly contacting the gate structure. 17 . The semiconductor device of claim 8 , further comprising: a second ILD layer on the first ILD layer, the first hard mask, and the second hard mask; and a contact plug passing through the second ILD layer, the first hard mask, and the second hard mask and directly contacting the gate structure. 18 . A semiconductor device, comprising: a substrate having a gate structure and a first ILD layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the second hard mask both contacting the gate structure directly. 19 . The semiconductor device of claim 18 , wherein the first hard mask comprises silicon nitride and the second hard mask comprises silicon oxide. 20 . The semiconductor device of claim 18 , further comprising: a second ILD layer on the first ILD layer, the first hard mask, and the second hard mask; and a contact plug passing through the second ILD layer and the second hard mask and directly contacting the gate structure.
Assignees
Inventors
Classifications
the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title
characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title
of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title
on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title
by forming self-aligned vias or self-aligned contact plugs · CPC title
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- What does patent US2016284641A1 cover?
- A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first h…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W20/42. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Sep 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).