Top level network and array level network for reconfigurable data processors

Patent metadata

Field	Value
Publication number	US-12306783-B2
Application number	US-202318199361-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	Jan 3, 2019
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system is connected to the array of configurable units. The bus system includes a top level network and an array level network. The top level network is connected to an external data interface for communication with memory outside of the array of configurable units. The array level network is connected to configurable units in the array of configurable units.

First claim

What is claimed is:

1. A reconfigurable data processor, comprising:
an array of configurable units;
a configurable interface unit including a configuration load controller; and
a bus system connected to the array of configurable units,
wherein the bus system includes a top level network and an array level network,
wherein the top level network is connected to an external data interface for communication with memory outside of the array of configurable units and to the configuration load controller,
wherein the array level network is connected to configurable units in the array of configurable units,
wherein the configurable interface unit including the configuration load controller is connected between the top level network and the array level network.

2. The reconfigurable data processor of claim 1 , wherein the configurable interface unit is further configured to comprise a memory access controller connected to the bus system.

3. The reconfigurable data processor of claim 2 , wherein the memory access controller includes logic to route data transfers between the top level network and the array level network.

4. The reconfigurable data processor of claim 1 , wherein the configuration load controller is configured to read a configuration file from the memory, and to send configuration data in the configuration file to the configurable units in the array of configurable units.

5. The reconfigurable data processor of claim 4 , wherein the configuration load controller is further configured to retrieve chunks of the configuration file over the top level network via the external data interface.

6. The reconfigurable data processor of claim 5 , wherein the configuration load controller is further configured to retrieve the chunks of the configuration file in ordered rounds.

7. The reconfigurable data processor of claim 4 , wherein the configuration load controller is further configured to distribute chunks of the configuration file to the configurable units in the array of configurable units on the array level network.

8. The reconfigurable data processor of claim 7 , wherein the configuration load controller is further configured to distribute the chunks of the configuration file in ordered rounds.

9. The reconfigurable data processor of claim 1 , wherein one or both of the array level network and the top level network comprise switches.

10. The reconfigurable data processor of claim 1 , wherein the reconfigurable data processor is implemented on a single integrated circuit or a single multichip module.

11. A reconfigurable data processor comprising:
an array of configurable units including a configurable interface unit;
an array level network connecting configurable units of the array of configurable units, including the configurable interface unit;
an interface circuit for communication through an external data connection of the reconfigurable data processor; and
a top level network, different than the array level network, connected between 4e the configurable interface unit of the array of configurable units and the interface circuit, wherein the configurable interface unit is connected between the top level network and the array level network.

12. The reconfigurable data processor of claim 11 , wherein the interface circuit comprises a memory controller and the external data connection comprises a connection to external memory.

13. The reconfigurable data processor of claim 11 , wherein the interface circuit comprises bus interface circuitry and the external data connection comprises an industry standard bus.

14. The reconfigurable data processor of claim 11 , the configurable interface unit comprising logic to route data transfers between the top level network and the array level network.

15. The reconfigurable data processor of claim 11 , wherein the configurable interface unit comprises a configuration load controller, the configuration load controller is further configured to read configuration data from a memory connected to the external data connection and to send the configuration data to the configurable units in the array of configurable units.

16. The reconfigurable data processor of claim 15 , wherein the configuration load controller is further configured to retrieve chunks of the configuration data over the top-level network via the interface circuit.

17. The reconfigurable data processor of claim 15 , wherein the configuration load controller is further configured to distribute chunks of the configuration data to the configurable units in the array of configurable units over the array level network.

18. The reconfigurable data processor of claim 11 , wherein one or both of the array level network and the top level network comprise switches.

19. The reconfigurable data processor of claim 11 , wherein the reconfigurable data processor is implemented on a single integrated circuit or a single multichip module.

Assignees

• Sambanova Systems Inc

Inventors

• Grohoski Gregory Frederick
• Jairath Sumti
• Luttrell Mark
• Prabhakar Raghu
• Sivaramakrishnan Ram
• Shah Manish K

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F15/7882

  for self reconfiguration · CPC title

• G06F15/7839

  with memory · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F12/10

  Address translation · CPC title