System level interconnect with programmable switching

Patent metadata

Field	Value
Publication number	US-9325320-B1
Application number	US-201313914308-A
Country	US
Kind code	B1
Filing date	Jun 10, 2013
Priority date	Apr 17, 2007
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A plurality of functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. A configuration data store in the integrated circuit stores configuration values loaded by the micro-controller. A plurality of connectors are configured to connect the integrated circuit to external signals. A programmable interconnect also located in the integrated circuit programmably connects together the plurality of functional elements and the plurality of connectors according to the configuration values loaded into the configuration data store.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of functional elements located in a same integrated circuit, wherein at least one of the functional elements comprises a micro-controller;
a configuration data store in the integrated circuit to store configuration values;
a plurality of I/O pins configured to connect the integrated circuit to external signals; and
a programmable interconnect, located in the integrated circuit, configured to programmably connect a first functional element of the plurality of functional elements to a first I/O pin of the plurality of I/O pins and to connect the first functional element to the micro-controller according to the configuration values loaded into the configuration data store.

2. The apparatus of claim 1 , wherein at least one of the plurality of functional elements comprises a programmable logic block.

3. The apparatus of claim 1 , wherein the plurality of functional elements comprises at least one of a timer, a counter, an interrupt controller, a direct memory access controller, input/output pins, a global clock, an external memory interface, a delta sigma analog to digital converter, a digital to analog converter, a serial communication block or a comparator.

4. The apparatus of claim 1 , wherein the programmable interconnect to further connect the first functional element to an interrupt controller and to a direct memory access controller.

5. The apparatus of claim 1 , wherein the programmable interconnect is configured to dynamically change the connections between the plurality of functional elements and the plurality of I/O pins during operation of the integrated circuit according to a plurality of operational states of the integrated circuit.

6. The apparatus of claim 1 , wherein:
the programmable interconnect is configured to operate the first I/O pins as an input pin by coupling the first I/O pin to an input for one of the plurality of functional elements while the integrated circuit is in a first operational state; and
the programmable interconnect is further configured to operate the first I/O pin as an output pin by coupling the first I/O pin to an output for one of the plurality of functional elements while the integrated circuit is in a second operational state.

7. The apparatus of claim 1 , wherein the programmable interconnect is configured to synchronously multiplex analog signals from the plurality of I/O pins to a same functional element that operates as an analog to digital converter.

8. The apparatus of claim 1 , wherein the programmable interconnect comprises horizontal channels configured to:
programmably couple to the plurality of functional elements according to the configuration values in the configuration data store; and
programmably couple to the plurality of I/O pins according to the configuration values in the configuration data store.

9. The apparatus of claim 1 , further comprising:
a first set of interface lines coupled to the plurality of associated functional elements; and
a second set of interface lines coupled to the plurality of associated I/O pins, the first and second sets of interface lines overlapping with a plurality of channel lines in associated channels of the programmable interconnect and programmably coupled to the plurality of channel lines according to the configuration values.

10. An integrated circuit, comprising:
a programmable interconnect configured to programmably couple a plurality of selectable functional elements to a plurality of selectable I/O pins in an integrated circuit according to configuration values, the programmable interconnect configured to be programmably changed in real-time while the integrated circuit is in operation,
wherein the programmable interconnect comprises a plurality of signal lines to connect to the plurality of selectable functional elements and a plurality of digital blocks in the programmable interconnect, the signal lines selectively coupled to the plurality of selectable functional elements, the plurality of selectable I/O pins, and the plurality of digital blocks according to the configuration values.

11. The integrated circuit of claim 10 , wherein at least one of the plurality of selectable functional elements comprises a programmable logic block.

12. The integrated circuit of claim 10 , wherein the plurality of functional elements comprises at least one of a micro-controller a timer, a counter, an interrupt controller, a direct memory access controller, input/output pins, a global clock, an external memory interface, a delta sigma analog to digital converter, a digital to analog converter, a serial communication block or a comparator.

13. The integrated circuit of claim 10 , wherein the programmable interconnect to further connect the first functional element to an interrupt controller and to a direct memory access controller.

14. The integrated circuit of claim 10 , further comprising:
an array of universal digital blocks comprising uncommitted programmable logic sections and structural arithmetic logic sections, the programmable interconnect programmably configured to connect the programmable logic sections and the arithmetic logic sections to the plurality of signal lines in the programmable interconnect.

15. An apparatus, comprising:
a plurality of functional elements comprising a micro-controller, a first peripheral, and a second peripheral, all located in a same integrated circuit;
a configuration data store in the integrated circuit to store configuration values;
a plurality of I/O pins configured to connect the integrated circuit to external signals; and
a programmable interconnect located in the integrated circuit to programmably connect the plurality of functional elements to the plurality of I/O pins according to the configuration values loaded into the configuration data store,
wherein the programmable interconnect is configured to be programmed according to the configuration values to couple a first I/O pin to the first peripheral while the integrated circuit is in a first state and couple the first I/O pin to the second peripheral when the integrated circuit is in a second state.

16. The apparatus of claim 15 , wherein at least one of the plurality of functional elements comprises a programmable logic block.

17. The apparatus of claim 15 , wherein the plurality of functional elements comprises at least one of a timer, a counter, an interrupt controller, a direct memory access controller, input/output pins, a global clock, an external memory interface, a delta sigma analog to digital converter, a digital to analog converter, a serial communication block or a comparator.

18. The apparatus of claim 15 , further comprising:
a first set of interface lines coupled to a plurality of associated functional elements; and
a second set of interface lines coupled to the plurality of associated I/O pins, the first and second sets of interface lines overlapping with a plurality of channel lines in associated channels of the programmable interconnect and programmably coupled to the plurality of channel lines according to the configuration values.

19. The apparatus of claim 15 , wherein the first peripheral comprises an analog peripheral.

20. The apparatus of claim 15 , wherein the second peripheral comprises a digital peripheral.

Assignees

• Cypress Semiconductor Corp

Inventors

• Sullam Bert
• Snyder Warren
• Mohammed Haneef

Classifications

• H03K19/17744 Primary

  for input/output signals · CPC title

• H03K19/177

  arranged in matrix form · CPC title

• H03K19/173 Primary

  using elementary logic circuits as components · CPC title

• H03K19/1776

  for memories · CPC title

• H03K19/17704

  the logic functions being realised by the interconnection of rows and columns · CPC title