Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric

Patent metadata

Field	Value
Publication number	US-2016188469-A1
Application number	US-201414583611-A
Country	US
Kind code	A1
Filing date	Dec 27, 2014
Priority date	Dec 27, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

First claim

What is claimed is:

1 . An interconnect apparatus, comprising:
a cache coherency tracker; a data interface to communicatively couple the cache coherency tracker to p cache-coherent agents, the data interface comprising n input buses, wherein n<p; and at least one multiplexer to selectively provide inputs from at least two of the cache-coherent agents to one of the input buses.

2 . The interconnect apparatus of claim 1 , wherein the multiplexer is a non-blocking multiplexer.

3 . The interconnect apparatus of claim 1 , wherein the multiplexer is a queueing multiplexer.

4 . The interconnect apparatus of claim 3 , wherein the queueing multiplexer comprises a first-in first-out queue.

5 . The interconnect apparatus of claim 1 , wherein the n input buses are to receive a first signal, and further comprising p non-multiplexed input buses to receive a second signal.

6 . The interconnect apparatus of claim 5 , wherein the p input buses to receive the second signal are of a substantially smaller data width than the n input buses to receive the first signal.

7 . The interconnect apparatus of claim 1 , further comprising p non-multiplexed output buses to provide a return signal.

8 . The interconnect apparatus of claim 7 , wherein the p non-multiplexed output buses are of a substantially smaller data width than the n input buses.

9 . A computing system, comprising:
p cache-coherent agents; at least one shared resource; and a shared fabric to communicatively couple the p cache-coherent agents to the at least one shared resource, comprising:
a cache coherency tracker;
a data interface to communicatively couple the cache coherency tracker to the p cache-coherent agents, the data interface comprising n input buses, wherein n<p; and
at least one multiplexer to selectively provide inputs from at least two of the cache-coherent agents to one of the input buses.

10 . The computing system of claim 9 , wherein the multiplexer is a non-blocking multiplexer.

11 . The computing system of claim 9 , wherein the multiplexer is a queueing multiplexer.

12 . The computing system of claim 11 , wherein the queueing multiplexer comprises a first-in first-out queue.

13 . The computing system of claim 9 , wherein the n input buses are to receive a first signal, and further comprising p non-multiplexed input buses to receive a second signal.

14 . The computing system of claim 13 , wherein the p input buses to receive the second signal are of a substantially smaller data width than the n input buses to receive the first signal.

15 . The computing system of claim 9 , further comprising p non-multiplexed output buses to provide a return signal.

16 . The computing system of claim 15 , wherein the p non-multiplexed output buses are of a substantially smaller data width than the n input buses.

17 . A method of maintaining cache coherency in a computing system, comprising:
receiving inputs from p cache-coherent agents; multiplexing the p inputs into n input buses, where p<n; and providing the p inputs to a shared fabric.

18 . The method of claim 17 , wherein multiplexing the p inputs comprises non-blocking multiplexing.

19 . The method of claim 17 , wherein multiplexing the p inputs comprises queuing the inputs.

20 . The method of claim 19 , wherein the queueing comprises first-in first-out queueing.

21 . The method of claim 17 , wherein the p inputs comprise a first signal, and further comprising receiving p non-multiplexed inputs comprising a second signal.

22 . The method of claim 17 , further comprising providing p non-multiplexed outputs.

Assignees

• Intel Corp

Inventors

• Nagarajan Ramadass
• Niell Jose S
• Klinglesmith Michael T
• Bachand Derek T
• Kumar Ganesh

Classifications

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F13/287 Primary

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title