Transposition operation device, integrated circuit for the same, and transposition method

US9201899B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9201899-B2
Application numberUS-201213824865-A
CountryUS
Kind codeB2
Filing dateSep 11, 2012
Priority dateOct 14, 2011
Publication dateDec 1, 2015
Grant dateDec 1, 2015

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Abstract

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A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.

First claim

Opening claim text (preview).

The invention claimed is: 1. A transposition operation device comprising: an operation circuit; a processor, the processor including a register group storing therein a matrix of data as a target for operation and composed of a plurality of registers, each register storing therein elements in a respective row of the matrix, wherein the elements in the respective row of the matrix are stored before transposition upon one instruction, and elements in a respective row of a transform…

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What does patent US9201899B2 cover?
A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the registe…
Who is the assignee on this patent?
Nishimura Takashi, Morishita Hiroyuki, Panasonic Ip Man Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F9/30032. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).