Execution pipeline data forwarding

Patent metadata

Field	Value
Publication number	US-9569214-B2
Application number	US-201213728765-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Dec 27, 2012
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.

First claim

The invention claimed is:

1. In an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit, the method comprising:
producing output data with the producing execution subunit;
consuming input data with the consuming execution subunit;
for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identity function in which the input to the one or more intervening operations is equal to the output of the one or more intervening operations; and
if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.

2. The method of claim 1 , where the evaluating of the one or more intervening operations includes determining whether the one or more intervening operations include a store instruction followed by a load instruction having a common memory address.

3. The method of claim 2 , where the load instruction immediately follows the store instruction in a next cycle of the execution pipeline.

4. The method of claim 1 , where the output data is forwarded directly to the consuming execution subunit at a point in time prior to the output data being available to a load/store portion of the execution pipeline that is to send the output data to the consuming execution subunit.

5. The method of claim 4 , where the load/store portion of the execution pipeline includes one or more of a store queue and a memory location in a cache, and the output data is forwarded directly to the consuming execution subunit at a point in time prior to the output data being available to a load/store portion of the execution pipeline that is to send the output data to the consuming execution subunit.

6. The method of claim 4 , further comprising:
overriding control by a scheduler that would otherwise control the execution pipeline to stall execution by the consuming execution subunit until the output data becomes available for use by the load/store portion of the execution pipeline to send to the consuming execution subunit.

7. The method of claim 4 , further comprising:
controlling the bypass network to send the output data received from the producing execution subunit to the load/store portion and the consuming execution subunit in parallel.

8. The method of claim 1 , where the bypass network includes one or more multiplexers operatively coupled to one or more of the execution subunits, and where controlling the bypass network includes providing an input to a select line of the one or more multiplexers to select the consuming execution subunit as a destination to forward the output data.

9. A micro-processing and memory system comprising:
an execution pipeline with a plurality of execution subunits, the execution subunits including a producing execution subunit configured to produce output data and a consuming execution subunit configured to consume input data;
a bypass network operatively coupled with the execution pipeline, the bypass network being configured to forward data produced by one execution subunit directly to another execution subunit; and
forwarding logic configured to, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, (i) evaluate those one or more intervening operations to determine whether their execution would compose an identity function in which the input to the one or more intervening operations is equal to the output of the one or more intervening operations; and (ii) if the one or more intervening operations would compose such an identity function, control the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.

10. The micro-processing and memory system of claim 9 , where the evaluation performed by the forwarding logic includes determining whether the one or more intervening operations include a store instruction followed by a load instruction having a common memory address.

11. The micro-processing and memory system of claim 10 , where the load instruction immediately follows the store instruction in a next cycle of the execution pipeline.

12. The micro-processing and memory system of claim 9 , where the output data is forwarded directly to the consuming execution subunit prior to the output data being available to a load/store portion of the execution pipeline that is to send the output data to the consuming execution subunit.

13. The micro-processing and memory system of claim 12 , where the load/store portion of the execution pipeline includes one or more of a store queue and a memory location in a cache, and where the output data is forwarded directly to the consuming execution subunit at a point in time prior to it being available in any of such store queue or memory location.

14. The micro-processing and memory system of claim 12 , where the forwarding logic is configured to control the bypass network to send the output data received from the producing execution subunit to the load/store portion and the consuming execution subunit in parallel.

15. The micro-processing and memory system of claim 9 , where the bypass network includes one or more multiplexers operatively coupled to one or more of the execution subunits, and the forwarding logic is operatively coupled to a select line of the one or more multiplexers to select the consuming execution subunit as a destination to forward the output data.

16. A micro-processing and memory system comprising:
an execution pipeline with a plurality of execution subunits, the execution subunits including a producing execution subunit configured to produce output data and a consuming execution subunit configured to consume input data;
a bypass network operatively coupled with the execution pipeline, the bypass network being configured to send data produced by one execution subunit directly to another execution subunit; and
forwarding logic configured to, for two or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, (i) detect whether those two or more intervening operations include a store instruction followed by a load instruction having a common memory address; and (ii) if the two or more intervening operations do include such a store and load instruction, control the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.

17. The micro-processing and memory system of claim 16 , where the load instruction immediately follows the store instruction in a next cycle of the execution pipeline.

18. The micro-processing and memory system of claim 16 , where the output data is forwarded directly to the consuming execution subunit at a time prior to the output data being available to a load/store portion of the execution pipeline that includes one or more of a store queue, and a memory location of a cache, and where the output data is forwarded directly to the consuming execution subunit at a point in time prior to it being available in any of such store queue or memory lo

Assignees

• Nvidia Corp

Inventors

• Govindu Gokul
• Gupta Parag
• Pitkethly Scott
• Rozas Guillermo J

Classifications

• G06F9/3826 Primary

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/30079 Primary

  Pipeline control instructions, e.g. multicycle NOP · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title