Matrix transposing circuit

Patent metadata

Field	Value
Publication number	US-2016012012-A1
Application number	US-201514662246-A
Country	US
Kind code	A1
Filing date	Mar 19, 2015
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

The disclosure provides a matrix transposing circuit for outputting a transposed N×N matrix. The matrix transposing circuit includes: an input resister array with m×N array; a memory having b storage blocks; an output register array with N×m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n×m×b. The matrix is divided into multiple sub-matrixes with m×n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.

First claim

What is claimed is:

1 . A matrix transposing circuit for transposing an N×N matrix into a transposed matrix of the matrix, comprising:
an m×N input register array;
a memory, having b storage blocks; and
an N×m output register array;
wherein N, m, n, b are integer in power of 2, and N=n×m×b,
wherein the matrix is divided into multiple sub-matrixes, each of the sub-matrixes has m×n entries, a plurality of the entries of the sub-matrixes form a Y matrix,
wherein the Y matrix is divided into b blocks according to value of b, and respectively stores multiple entry data of the sub-matrixes of the b blocks corresponding to the b storage blocks,
wherein the input resister receives the entry data along a first shifting direction and outputs data to the b storage blocks along a second shifting direction for corresponding storing the data into the b storage blocks,
wherein the output resister array receives the entry data from the b storage blocks along the first shifting direction and outputs the entry data corresponding to the transposed matrix along the second shifting direction.

2 . The matrix transposing circuit as claimed in claim 1 , wherein the input register array sequentially receives m 1×N row vectors of the matrix along the first shifting direction, stores entries of the row vectors in the corresponding b storage blocks along the second shifting direction after the input register array is filled, and receives following N−m 1×N row vectors of the matrix.

3 . The matrix transposing circuit as claimed in claim 2 , wherein the input register array comprises m×(N/n) registers,
wherein input end and output end of the each register of the input register array have n data ports, the m×(N/n) registers are divided into b sub-register arrays, and each of the sub-register arrays has the m×m registers,
wherein each of the sub-register arrays of the input register array receives data along the first shifting direction, and switches to the second shifting direction after all of the input register array is filled, wherein data outputted from the b sub-register arrays are stored in the b storage blocks along the second shifting direction.

4 . The matrix transposing circuit as claimed in claim 2 , wherein the output register array receives data from the b storage blocks along the first shifting direction and outputs entry data corresponding to the transposed matrix along the second shifting direction after the input register array is filled, and receives following data from the b storage blocks.

5 . The matrix transposing circuit as claimed in claim 4 , wherein the output register array comprises (N/m)×n registers,
wherein input end and output end of the each register of the output register array have m data ports, the (N/m)×n registers are divided into b sub-register arrays, and each of the sub-register arrays has the N×N registers,
wherein each of the sub-register arrays of the output register array receives data along the first shifting direction, and switches to the second shifting direction after all of the output register array is filled, and receives b-tuple data from b-bank RAM simultaneously and pushes the b-tuple data into the b sub-register arrays.

6 . The matrix transposing circuit as claimed in claim 1 , wherein N=16, m=2, n=4, and b=2.

7 . The matrix transposing circuit as claimed in claim 6 , wherein the Y matrix is a 8×4 matrix, Y i,j(=1, 2, . . . , 8, j=1,2,3,4) represent entries of the Y matrix, and the Y matrix is divided into a first block and a second block according to the b value, and entries of the first block are {Y i,j , i=1-4,j=1,2; and Y i , i=5-8, j=3,4} and entries of the second block are {Y i,j , i=1-4,j=2,3; and Y i,j , i=5-8, j=1,2}.

8 . The matrix transposing circuit as claimed in claim 6 , wherein the Y matrix is a 8×4 matrix, Y i,j(=1, 2, 8, j=1,2,3,4) represent entries of the Y matrix, and the Y matrix is divided into a first block and a second block according to the b value, and entries of the first block are {Y i,j , i=1,2,j=1,2; Y i,j , i=3,4, j=3,4; Y i,j , i=5,6, j=1,2; and Y i,j , i=7,8, j=3,4 } and the second block is remaining part of the Y matrix.

9 . The matrix transposing circuit as claimed in claim 6 , wherein the Y matrix is a 8×4 matrix, Y i,j(=1,2, 8, j=1,2,3,4) represent entries of the Y matrix, and the Y matrix is divided into a first block and a second block according to the b value, and entries of the first block are {Y i,j , i=1, j=1,2; Y i,j , i=2, j=3,4; Y i,j , i=3, j=1,2; Y i,j , i=4, j=3,4; Y i,j , i=5, j=1,2; Y i,j , i=6, j=3,4; i=7 j=1,2; Y i,j , i=8, j=3,4} and the second block is remaining part of the Y matrix.

10 . The matrix transposing circuit as claimed in claim 6 , wherein the Y matrix is a 8×4 matrix, Y i,j(=1,2, . . . 8, j=1,2,3,4) represent entries of the Y matrix, and the Y matrix is divided into a first block and a second block according to the b value, and entries of the first block are {Y i,j , i=1-4 j=1,3; Y i,j , i=5-8, j=2,4} and the second block is remaining part of the Y matrix.

11 . The matrix transposing circuit as claimed in claim 1 , wherein N=16, m=4, n=4, and b=1.

12 . The matrix transposing circuit as claimed in claim 1 , wherein a first transform is performed by the input register array when entries of the matrix are stored into the memory and a second transform is performed by the output register array when the entries of the matrix are received from the memory.

Assignees

• Ind Tech Res Inst

Inventors

• Yen Chih-Hsu
• Jou Fan-Di

Classifications

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C19/38

  two-dimensional [2D], e.g. horizontal and vertical shift registers · CPC title

• G11C7/106

  Data output latches · CPC title