TSV process window and fill performance enhancement by long pulsing and ramping

Patent metadata

Field	Value
Publication number	US-12305307-B2
Application number	US-202117758496-A
Country	US
Kind code	B2
Filing date	Jan 8, 2021
Priority date	Jan 10, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method of electroplating metal into features of a partially fabricated electronic device on a substrate having high open area portions is provided. The method includes initiating a bulk electrofill phase with a pulse at a high level of current; reducing the current to a baseline current level; and optionally increasing the current in one or more steps until electroplating is complete.

First claim

What is claimed is:

1. A method of electroplating metal, the method comprising:
contacting a substrate with an electroplating solution having ions of a metal, wherein the substrate has features providing an open area of at least 0.9% on a face of the substrate;
applying an electrofill current waveform to the substrate contacting the electroplating solution, wherein the electrofill current waveform comprises (i) a pulse having a magnitude of at least 2 times a magnitude of a baseline current fora duration of from 10 to 200 seconds, wherein the pulse of the electrofill current waveform comprises an initial step change that increases the magnitude of current applied to the substrate, followed by a ramp that decreases the magnitude of current applied to the substrate, wherein the duration of the ramp is at least 10 seconds, and (ii) a constant current step having, on average, the magnitude of the baseline current, wherein the constant current step follows the pulse; and
filling at least a portion of the features with the metal.

2. The method of claim 1 , wherein the ramp is a linear change between the magnitude of the pulse current and the magnitude of the baseline current.

3. The method of claim 1 , wherein the electrofill current waveform further comprises (iii) a second constant current step having, on average, a magnitude that is greater than the magnitude of the baseline current.

4. The method of claim 1 , wherein the electrofill current waveform further comprises (iv) one or more additional constant current steps, each having, on average, a magnitude that is greater than the magnitude of the baseline current.

5. The method of claim 1 , wherein the electrofill current waveform further comprises an induction phase preceding the pulse, wherein during the induction phase no current is applied to the substrate or an induction phase current is applied to the substrate, wherein the induction phase current has an average magnitude of between 30 mA and 200 mA.

6. The method of claim 1 , wherein, when applied to the substrate, the baseline current produces a current density of between 0.1 and 10 mA/cm 2 on the substrate.

7. The method of claim 1 , wherein the substrate is a semiconductor wafer having integrated circuits at least partially fabricated thereon.

8. The method of claim 1 , wherein the substrate is a 300 mm semiconductor wafer.

9. The method of claim 1 , wherein the features on the substrate are through silicon vias.

10. The method of claim 9 , wherein the through silicon vias have, on average, an opening width or diameter on the substrate face of at least 0.1 micrometers.

11. The method of claim 9 , wherein the through silicon vias have, on average, a depth of at least 10 micrometers.

12. The method of claim 9 , wherein the through silicon vias have, on average, an aspect ratio of 4 or greater.

13. The method of claim 1 , wherein the metal is copper.

14. The method of claim 1 , wherein the electroplating solution comprises a source of cupric ions.

15. The method of claim 1 , wherein the electroplating solution does not contain a source of cuprous ions.

16. The method of claim 1 , wherein the electroplating solution has a pH of 0 to 1.

17. The method of claim 1 , wherein the electroplating solution comprises an accelerator and a suppressor.

18. The method of claim 17 , wherein the accelerator is SPS.

19. A method of electroplating metal, the method comprising:
contacting a substrate with an electroplating solution having ions of a metal, wherein the substrate has features;
applying an electrofill current waveform to the substrate contacting the electroplating solution, wherein the electrofill current waveform comprises (i) a pulse having a magnitude of at least 2 times a magnitude of a baseline current for a duration of from 10 to 200 seconds, wherein the pulse of the electrofill current waveform comprises an initial step change that increases the magnitude of current applied to the substrate, followed by a ramp that decreases the magnitude of current applied to the substrate, wherein the duration of the ramp is at least 10 seconds, and (ii) a constant current step having, on average, the magnitude of the baseline current, wherein the constant current step follows the pulse; and
filling at least a portion of the features with the metal.

20. An electroplating system for electroplating metal,
the system comprising:
an electroplating cell configured to contain an anode and an electroplating solution having ions of a metal;
a wafer holder configured to support a substrate within the electroplating cell; and
one or more controllers configured to cause:
contacting the substrate with the electroplating solution having ions of a metal, wherein the substrate has features;
applying an electrofill current waveform to the substrate contacting the electroplating solution, wherein the electrofill current waveform comprises (i) a pulse having a magnitude of at least 2 times a magnitude of a baseline current for a duration of from 10 to 200 seconds, wherein the pulse of the electrofill current waveform comprises an initial step change that increases the magnitude of current applied to the substrate, followed by a ramp that decreases the magnitude of current applied to the substrate, wherein the duration of the ramp is at least 10 seconds, and (ii) a constant current step having, on average, the magnitude of the baseline current, wherein the constant current step follows the pulse; and
filling at least a portion of the features with the metal.

21. The system of claim 20 , wherein the ramp is a linear change between the magnitude of the pulse current and the magnitude of the baseline current.

22. The system of claim 20 , wherein the electrofill current waveform further comprises (iii) a second constant current step having, on average, a magnitude that is greater than the magnitude of the baseline current.

23. The system of claim 20 , wherein the electrofill current waveform further comprises (iv) one or more additional constant current steps, each having, on average, a magnitude that is greater than the magnitude of the baseline current.

24. The system of claim 20 , wherein the electrofill current waveform further comprises an induction phase preceding the pulse, wherein during the induction phase no current is applied to the substrate or an induction phase current is applied to the substrate, wherein the induction phase current has an average magnitude of between 30 mA and 200 mA.

25. The system of claim 20 , wherein, when applied to the substrate, the baseline current produces a current density of between about 0.1 and 10 mA/cm 2 on the substrate.

26. The system of claim 20 , wherein the substrate is a semiconductor wafer having integrated circuits at least partially fabricated thereon.

27. The system of claim 20 , wherein the features on the substrate are through silicon vias.

28. The system of claim 27 , wherein the through silicon vias have, on average, an opening width or diameter on the substrate face of at least 0.1 micrometers.

29. The system of claim 27 , wherein the through silicon vias have, on average, a depth of at least 10 micrometers.

30. The system of claim 27 , wherein the through silicon vias have, on average, an aspect ratio of 4 or greater.

31. The system of claim 20 , wherein the m

Assignees

• Lam Res Corp

Inventors

• Shin Jae
• Richardson Joseph
• Velmurugan Jeyavel
• Ponnuswamy Thomas Anand
• Mayer Steven T

Classifications

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/043 Primary

  for electroplating · CPC title

• H10P14/47 Primary

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title