Leakage current reduction in electrical isolation gate structures

Patent metadata

Field	Value
Publication number	US-12278232-B2
Application number	US-202217930188-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Oct 10, 2018
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first diffusion region of a first conductivity type, wherein:
the first diffusion region includes a plurality of active regions;
respective active regions of the plurality of active regions include respective pluralities of transistors;
a threshold voltage of a given respective plurality of transistors is dependent on a plurality of layers of materials in gate stacks of the given respective plurality of transistors and is further dependent on an order of the plurality of layers of materials;
a first active region of the plurality of active regions and a second active region of the plurality of active regions are separated by a single diffusion break isolation; and
the single diffusion break isolation includes a single transistor having a second threshold voltage greater than threshold voltages of transistors in the first active region and the second active region, wherein the single transistor has a single gate stack formed from a second plurality of layers of materials, wherein the second threshold voltage is dependent on the second plurality of layers of materials and the order of the second plurality of layers, wherein there is at least one difference between the plurality of layers of materials and the second plurality of layers of materials.

2. The integrated circuit as recited in claim 1 further comprising a second diffusion region of a second conductivity type different than the first conductivity type, wherein the second diffusion region is separated from the first diffusion region using a fabrication technique different from the single diffusion break isolation.

3. The integrated circuit as recited in claim 2 wherein the fabrication technique is shallow trench isolation.

4. The integrated circuit as recited in claim 1 wherein a first leakage current in the single transistor is less than a second leakage current in a given transistor of the respective pluralities of transistors in the plurality of active regions.

5. The integrated circuit as recited in claim 1 wherein the single gate stack is coupled to a fixed voltage input during operation that ensures that the single transistor is off during operation.

6. The integrated circuit as recited in claim 1 further comprising:
a second diffusion region of a second conductivity type different from the first conductivity type, wherein:
the second diffusion region includes a second plurality of active regions;
respective second active regions of the second plurality of active regions include respective second pluralities of transistors;
a third threshold voltage of a given second respective plurality of transistors is dependent on a third plurality of layers of materials in gate stacks of the given second respective plurality of transistors and is further dependent on an order of the third plurality of layers of materials;
a third active region of the plurality of active regions and a fourth active region of the second plurality of active regions are separated by a second single diffusion break isolation; and
the second single diffusion break isolation includes a second single transistor having a third threshold voltage greater than threshold voltages of transistors in the third active region and the fourth active region, wherein the second single transistor has a second single gate stack formed from a fourth plurality of layers of materials, wherein the third threshold voltage is dependent on the fourth plurality of layers of materials and the order of the fourth plurality of layers, wherein there is at least one difference between the third plurality of layers of materials and the fourth plurality of layers of materials.

7. The integrated circuit as recited in claim 6 wherein a third leakage current in the second single transistor is less than a fourth leakage current in a given transistor of the second respective pluralities of transistors in the second plurality of active regions.

8. The integrated circuit as recited in claim 6 wherein the second single gate stack is coupled to a second fixed voltage input during operation that ensures that the second single transistor is off during operation.

9. The integrated circuit as recited in claim 8 wherein the second fixed voltage input is different from a first fixed voltage input to which the single gate stack in the single diffusion break isolation is coupled during operation.

10. The integrated circuit as recited in claim 1 wherein the respective pluralities of transistors and the single transistor are fin field effect transistors (FinFETs).

11. An integrated circuit comprising:
a first diffusion region of a first conductivity type, wherein:
the first diffusion region includes a plurality of active regions;
respective active regions of the plurality of active regions include respective pluralities of transistors;
a given respective plurality of transistors comprise gates stacks formed from a plurality of layers of materials in a particular order;
a first active region of the plurality of active regions and a second active region of the plurality of active regions are separated by a single diffusion break isolation; and
the single diffusion break isolation includes a single transistor, wherein the single transistor has a single gate stack formed from a second plurality of layers of materials, wherein there is at least one difference between the plurality of layers of materials and the second plurality of layers of materials, and wherein the at least one difference is at least one of an order of the second plurality of layers of materials and a type of material in a given layer of the second plurality of layers of materials.

12. The integrated circuit as recited in claim 11 further comprising a second diffusion region of a second conductivity type different than the first conductivity type, wherein the second diffusion region is separated from the first diffusion region using a fabrication technique different from the single diffusion break isolation.

13. The integrated circuit as recited in claim 12 wherein the fabrication technique is shallow trench isolation.

14. The integrated circuit as recited in claim 11 wherein a first leakage current in the single transistor is less than a second leakage current in a given transistor of the respective pluralities of transistors in the plurality of active regions.

15. The integrated circuit as recited in claim 11 wherein the single gate stack is coupled to a fixed voltage input during operation that ensures that the single transistor is off during operation.

16. The integrated circuit as recited in claim 11 further comprising:
a second diffusion region of a second conductivity type different from the first conductivity type, wherein:
the second diffusion region includes a second plurality of active regions;
respective second active regions of the second plurality of active regions include respective second pluralities of transistors;
a given second respective plurality of transistors comprise gate stacks formed from a third plurality of layers of materials;
a third active region of the plurality of active regions and a fourth active region of the second plurality of active regions are separated by a second single diffusion break isolation; and
the second single diffusion break isolation includes a second single transistor, wherein the second single transistor has a second single gate stack formed from a fourth plurality of layers of materials, wherein there is at least one difference between the third plurality of layers of materials and the fourth plurality of lay

Assignees

• Apple Inc

Inventors

• Alptekin Emre
• Hoffmann Thomas

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title