Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9876013-B1
Application number	US-201715477554-A
Country	US
Kind code	B1
Filing date	Apr 3, 2017
Priority date	Aug 24, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A semiconductor device is provided including first and second active fin arrays on a substrate. The semiconductor device further includes a pair of first gate spacers disposed on the first and second active fin arrays, each of the pair of first gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and first and second gate electrodes, the first gate electrode disposed between the first regions and the second gate electrode disposed between the second regions. The first regions are on the first active fin array, the second regions are on the second active fin array, and the third regions are between the first active fin array and the second active fin array. Each of the first and second widths is greater than the third width.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active fin array and a second active fin array, the first and second active fin arrays being disposed on a substrate extending in a first direction and spaced apart from each other in a second direction crossing the first direction;
a pair of first gate spacers disposed on the first and second active fin arrays extending in the second direction, each of the pair of first gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and
first and second gate electrodes spaced apart from each other, the first gate electrode disposed between the first regions of the pair of first gate spacers and the second gate electrode disposed between the second regions of the pair of first gate spacers,
wherein the first regions of the pair of first gate spacers are disposed on the first active fin array, the second regions of the pair of first gate spacers are disposed on the second active fin array, and the third regions of the pair of first gate spacers are disposed between the first active fin array and the second active fin array; and
wherein each of the first and second widths is greater than the third width.

2. The semiconductor device of claim 1 , further comprising an insulator between the third regions of the pair of first gate spacers.

3. The semiconductor device of claim 2 , wherein the insulator is in contact with the first gate electrode, the second gate electrode, and the third regions of the pair of first gate spacers.

4. The semiconductor device of claim 2 , wherein the insulator includes a first portion between the first region of each of the pair of first gate spacers and the second region of each of the pair of first gate spacers, and a second portion between the first gate electrode and the second gate electrode.

5. The semiconductor device of claim 2 ,
wherein the first gate electrode overlaps the first active fin array and does not overlap the second active fin array;
wherein the second gate electrode overlaps the second active fin array and does not overlap the first active fin array; and
wherein the insulator does not overlap the first and second active fin arrays.

6. The semiconductor device of claim 2 , further comprising a field insulation film disposed on the substrate to cover at least a part of the first and second active fin arrays,
wherein a bottom surface of the insulator is disposed to be in contact with the field insulation film.

7. The semiconductor device of claim 1 , further comprising:
a first gate insulation film disposed between the first region of the pair of first gate spacers and the first gate electrode and disposed on sidewalls of the first region; and
a second gate insulation film disposed between the second region of the pair of first gate spacers and the second gate electrode and disposed on sidewalls of the second region,
wherein the first and second gate insulation films are not disposed between the first gate electrode and an insulator, between the second gate electrode and the insulator, and on sidewalls of the third regions of the pair of first gate spacers.

8. The semiconductor device of claim 1 , further comprising a pair of second gate spacers extending in the second direction and disposed on the first and second active fin arrays to be spaced apart from the pair of first gate spacers in the first direction,
wherein each of the pair of second gate spacers has a fourth width which is greater than the third width.

9. A semiconductor device, comprising:
a first active fin array and a second active fin array, the first and second active fin arrays being on a substrate extending in a first direction and spaced apart from each other in a second direction crossing the first direction;
a first gate electrode overlapping the first active fin array and not overlapping the second active fin array;
a second gate electrode overlapping the second active fin array and not overlapping the first active fin array that is spaced apart from the first gate electrode in the second direction;
an insulator between the first gate electrode and the second gate electrode;
a first gate spacer on a first sidewall of the first gate electrode, a first sidewall of the second gate electrode and a first sidewall of the insulator;
a second gate spacer on a second sidewall of the first gate electrode; and
a third gate spacer on a second sidewall of the second gate electrode,
wherein the first gate spacer includes a first recess formed on an inner sidewall of the first gate spacer; and
wherein a part of the insulator is inserted into the first recess.

10. The semiconductor device of claim 9 :
wherein the first gate electrode includes a first surface connecting both sidewalls of the first gate electrode and facing the second gate electrode;
wherein the second gate electrode includes a second surface connecting both sidewalls of the second gate electrode and facing the first surface; and
wherein the insulator is in contact with the first surface and the second surface.

11. The semiconductor device of claim 9 , wherein a width of a first region of the first gate spacer disposed on the first sidewall of the first gate electrode and a width of a second region of the first gate spacer disposed on the first sidewall of the second gate electrode are greater than a width of a third region of the first gate spacer disposed on the first sidewall of the insulator.

12. The semiconductor device of claim 11 , further comprising a fourth gate spacer disposed on the second sidewall of the insulator,
wherein a width of the fourth gate spacer is different from the width of the third region of the first gate spacer.

13. The semiconductor device of claim 9 , further comprising a fourth gate spacer disposed on the second sidewall of the insulator,
wherein the fourth gate spacer includes a second recess formed in an inner sidewall of the fourth gate spacer; and
wherein a remaining portion of the insulator is inserted in the second recess.

14. The semiconductor device of claim 13 , wherein a width of a portion of the first gate spacer disposed on the first sidewall of the insulator is different from the width of the fourth gate spacer.

15. The semiconductor device of claim 9 , wherein the insulator does not overlap the first and second active fin arrays.

16. A semiconductor device, comprising:
first and second active fin arrays on a substrate extending in a first direction and spaced apart from each other in a second direction crossing the first direction;
first and second gate spacers on the first and second active fin arrays extending in the second direction, each of the first and second gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and
wherein each of the first and second widths is greater than the third width.

17. The device of claim 16 , further comprising first and second gate electrodes spaced apart from each other, the first gate electrode disposed between the first regions of the first and second gate spacers and the second gate electrode disposed between the second regions of the first and second gate spacers,
wherein the first regions of the first and second gate spacers are disposed on the first active fin array, the second regions of the first and second gate spacers are disposed on the second active fin a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Seung Ju
• Lee Jeong Yun
• Min Kyung Seok
• Seong Geum Jung
• Lim Bo Ra
• Hong Seung Soo

Classifications

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic