Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure

Patent metadata

Field	Value
Publication number	US-9570442-B1
Application number	US-201615133832-A
Country	US
Kind code	B1
Filing date	Apr 20, 2016
Priority date	Apr 20, 2016
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

First claim

What is claimed is:

1. A Fin field-effect transistor (FET) (FinFET)-based circuit, comprising:
a semiconductor substrate;
a Fin formed from the semiconductor substrate;
a first FinFET corresponding to the Fin;
a second FinFET corresponding to the Fin;
a gate region disposed between the first FinFET and the second FinFET; and
a self-aligned single diffusion break (SDB) isolation structure formed in the Fin between the first FinFET and the second FinFET and self-aligned with the gate region, wherein the self-aligned SDB isolation structure electrically isolates the first FinFET and the second FinFET and applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

2. The FinFET-based circuit of claim 1 , wherein the self-aligned SDB isolation structure comprises an SDB trench etched into the Fin, the SDB trench filled with a dielectric material.

3. The FinFET-based circuit of claim 2 , further comprising:
a first spacer disposed adjacent to the gate region; and
a second spacer disposed adjacent to the gate region opposite the first spacer,
wherein the SDB trench is formed between the first spacer and the second spacer.

4. The FinFET-based circuit of claim 3 , wherein the dielectric material of the self-aligned SDB isolation structure is planar with a top surface of a gate corresponding to the first FinFET.

5. The FinFET-based circuit of claim 2 , wherein the first FinFET comprises a first N-type FinFET and the second FinFET comprises a second N-type FinFET.

6. The FinFET-based circuit of claim 5 , wherein the dielectric material disposed in the SDB trench comprises porous silicon dioxide such that the SDB trench applies tensile stress to a first channel of the first N-type FinFET and to a second channel of the second N-type FinFET.

7. The FinFET-based circuit of claim 2 , wherein the first FinFET comprises a first P-type FinFET and the second FinFET comprises a second P-type FinFET.

8. The FinFET-based circuit of claim 7 , wherein the dielectric material disposed in the SDB trench comprises a layer of silicon buried by silicon dioxide such that the SDB trench applies compressive stress to a first channel of the first P-type FinFET and to a second channel of the second P-type FinFET.

9. The FinFET-based circuit of claim 7 , wherein the dielectric material disposed in the SDB trench comprises a layer of silicon buried by silicon nitride such that the SDB trench applies compressive stress to a first channel of the first P-type FinFET and to a second channel of the second P-type FinFET.

10. The FinFET-based circuit of claim 1 , wherein:
the first FinFET comprises a first N-type FinFET and the second FinFET comprises a second N-type FinFET; and
the FinFET-based circuit further comprises:
a second Fin formed from the semiconductor substrate;
a first P-type FinFET corresponding to the second Fin;
a second P-type FinFET corresponding to the second Fin;
a second gate region disposed between the first P-type FinFET and the second P-type FinFET; and
a second self-aligned SDB isolation structure formed in the second Fin between the first P-type FinFET and the second P-type FinFET and self-aligned with the second gate region, wherein the second self-aligned SDB isolation structure electrically isolates the first P-type FinFET and the second P-type FinFET and applies stress to a first P-type channel corresponding to the first P-type FinFET and to a second P-type channel corresponding to the second P-type FinFET.

11. The FinFET-based circuit of claim 10 , wherein:
the self-aligned SDB isolation structure comprises a first SDB trench etched into the Fin, the first SDB trench filled with a first dielectric material; and
the second self-aligned SDB isolation structure comprises a second SDB trench etched into the second Fin, the second SDB trench filled with a second dielectric material different from the first dielectric material.

12. The FinFET-based circuit of claim 1 integrated into an integrated circuit (IC).

13. The FinFET-based circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

14. A Fin field-effect transistor (FET) (FinFET)-based circuit, comprising:
a means for providing a semiconductor substrate;
a means for forming a Fin from the semiconductor substrate;
a means for forming a first FinFET corresponding to the Fin;
a means for forming a second FinFET corresponding to the Fin;
a means for disposing a gate region between the first FinFET and the second FinFET; and
a means for forming a self-aligned single diffusion break (SDB) isolation structure in the Fin between the first FinFET and the second FinFET and self-aligned with the gate region, wherein the self-aligned SDB isolation structure electrically isolates the first FinFET and the second FinFET and applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

15. A method of fabricating a Fin field-effect transistor (FET) (FinFET)-based circuit, comprising:
providing a semiconductor substrate comprising a Fin formed from the semiconductor substrate, a first FinFET corresponding to the Fin, a second FinFET corresponding to the Fin, and a gate region disposed between the first FinFET and the second FinFET; and
forming a self-aligned single diffusion break (SDB) isolation structure in the Fin between the first FinFET and the second FinFET and self-aligned with the gate region, wherein the self-aligned SDB isolation structure electrically isolates the first FinFET and the second FinFET and applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

16. The method of claim 15 , further comprising:
disposing an oxide hard mask layer comprising an opening aligned with the gate region;
etching a polysilicon layer and a gate oxide layer aligned with the opening; and
removing the oxide hard mask layer.

17. The method of claim 15 , wherein forming the self-aligned SDB isolation structure comprises:
etching an SDB trench in the Fin corresponding to the gate region such that the SDB trench is self-aligned with the gate region; and
disposing a dielectric material in the SDB trench.

18. The method of claim 17 , wherein the disposing the dielectric material comprises disposing the dielectric material to be planar with a top surface of a gate of the first FinFET.

19. The method of claim 17 , wherein providing the semiconductor substrate comprises providing the semiconductor substrate wherein the first FinFET comprises a first N-type FinFET and the second FinFET comprises a second N-type FinFET.

20. The method of claim 19 , wherein disposing the dielectric material in the SDB trench comprises disposing porous silicon dioxide in the SDB trench such that the SDB trench applies tensile stress to a first channel of the first N-type FinFET and to a second channe

Assignees

• Qualcomm Inc

Inventors

• Liu Yanxiang
• Yuan Jun

Classifications

• H01L21/823462

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic