Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9922979-B2
Application number	US-201615014928-A
Country	US
Kind code	B2
Filing date	Feb 3, 2016
Priority date	Mar 25, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a substrate including a fin-type active region formed in the substrate,
the fin-type active region protruding from the substrate and extending in a first direction parallel to a main surface of the substrate,
the fin-type active region including a channel region having a first conductivity type,
the fin-type active region including a stepped portion on at least one sidewall thereof;

a step insulation layer on the at least one sidewall of the fin-type active region,
the step insulation layer contacting the stepped portion of the fin-type active region; and

a first high-level isolation layer on the at least one sidewall of the fin-type active region with the step insulation layer between the first high-level isolation layer and the at least one sidewall of the fin-type active region,
the first high-level isolation layer extending in a second direction that is different from the first direction.

2. The IC device of claim 1 , wherein a top surface of the step insulation layer is at a level that is equal to or higher than a top surface of the fin-type active region.

3. The IC device of claim 1 , wherein a top surface of the first high-level isolation layer is at a level that is higher than or equal to a top surface of the fin-type active region.

4. The IC device of claim 1 , further comprising:
a first low-level isolation layer on a lower sidewall of the fin-type active region, wherein
the first low-level isolation layer extends in the first direction, and
a top surface of the first low-level isolation layer is at a level that is lower than a top surface of the fin-type active region.

5. The IC device of claim 1 , further comprising:
a first low-level isolation layer on a lower sidewall of the fin-type active region, wherein a top level of the first high-level isolation layer is higher than a top level of the first low-level isolation layer.

6. The IC device of claim 1 , wherein at least one of the step insulation layer and the first high-level isolation layer include an oxide capable of applying a tensile stress to the fin-type active region.

7. The IC device of claim 1 , wherein the step insulation layer includes:
an insulation liner on the at least one sidewall of the fin-type active region, the insulation liner contacting the stepped portion of the fin-type active region; and
a gap-fill insulating layer between the insulation liner and the first high-level isolation layer.

8. The IC device of claim 1 , further comprising:
a normal gate on the fin-type active region; and
a first dummy gate on the first high-level isolation layer, wherein
the normal gate and the first dummy gate each extend in the second direction, and
the second direction is different than the first direction.

9. The IC device of claim 1 , wherein the channel region is an NMOS channel region.

10. The IC device of claim 1 , wherein
the fin-type active region includes two first sidewalls and two second sidewalls,
the two first sidewalls extend in the first direction,
the two second sidewalls extend in the second direction,
the first sidewalls have a first width,
the second sidewalls have a second width that is less than the first width, and
the stepped portion is formed in at least one of the two second sidewalls of the fin-type active region.

11. The IC device of claim 10 , wherein the stepped portion is formed in each of the two second sidewalls of the fin-type active region.

12. An IC device comprising:
a substrate including one pair of first fin-type active regions and one pair of second fin-type active regions,
the first fin-type active regions having a first-conductivity-type channel region,
the first fin-type active regions being formed in a straight line in a first region of the substrate,
the second fin-type active regions having a second-conductivity-type channel region,
the second fin-type active regions being formed in a straight line in a second region of the substrate,
at least one first fin-type active region of the one pair of first fin-type active regions including a stepped portion on one sidewall thereof;
a first high-level isolation layer on the substrate between the one pair of first fin-type active regions;
a step insulation layer on the substrate between the at least one first fin-type active region and the first high-level isolation layer,
the step insulation layer contacting the stepped portion; and

a second high-level isolation layer on the substrate between the one pair of second fin-type active regions.

13. The IC device of claim 12 , wherein a top surface of the first high-level isolation layer is at a higher level than a top surface of the second high-level isolation layer.

14. The IC device of claim 12 , further comprising:
at least one first normal gate on the one pair of first fin-type active regions and extending in a direction that intersects an extension direction of the one pair of first fin-type active regions;
at least one first dummy gate on at least a portion of the first high-level isolation layer and extending in a direction parallel to the at least one first normal gate;
at least one second normal gate on the one pair of second fin-type active regions and extending in a direction that intersects an extension direction of the one pair of second fin-type active regions; and
at least one second dummy gate on at least a portion of the second high-level isolation layer and extending in a direction parallel to the at least one second normal gate.

15. The IC device of claim 14 , wherein a bottom surface of the at least one first dummy gate is at a higher level than a bottom surface of the at least one second dummy gate.

16. An integrated circuit (IC) device comprising:
a substrate including a plurality of first fin-type active regions formed in the substrate,
the first fin-type active regions being defined by first and second trenches formed in the substrate,
the first trenches and second trenches extending in first and second directions, respectively, that cross each other,
the first fin-type active regions being elongated in the first direction,
the first fin-type active regions each including a pair of first sidewalls opposite each other in the first direction and a pair of second sidewalls opposite each other in the second direction,
at least one of the second sidewalls including a stepped portion,
the first fin-type active regions each including a lower portion below the stepped portion and an upper portion that protrudes above the stepped portion;

a first high-level isolation layer in the second trenches; and
a step insulation layer on the stepped portion,
the step insulation layer between the first high-level isolation layer and the upper portions of the first fin-type active regions.

17. The IC device of claim 16 , further comprising:
a gate structure extending in the second direction and crossing over the first fin-type active regions, wherein
the first fin-type active regions include a NMOS channel between source and drain regions,
the gate structure crossing over the NMOS channel, and
the gate structure including a gate electrode on a gate insulating layer.

18. The IC device of claim 16 , further comprising:
a dummy gate extending in the second direction, wherein
the dummy gate crosses over the stepped portions in the first fin-type active regions.

19. The IC device of claim 16 , wherein each of the second sidewalls in the first fin-type active regions include the st

Assignees

• Chung Jae Yup
• Yoon Jong Shik
• Rhee Hwa Sung
• Jeong Hee Don
• Yoo Je Min
• Cha Kyu Man
• Youn Jong Mil
• Kim Hyun Jo
• Samsung Electronics Co Ltd

Inventors

• Chung Jae-Yup
• Yoon Jong-Shik
• Rhee Hwa-Sung
• Jeong Hee-Don
• Yoo Je-Min
• Cha Kyu-Man
• Youn Jong-Mil
• Kim Hyun-Jo

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title