Method of manufacturing a semiconductor device

US12265332B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12265332-B2
Application numberUS-202117491743-A
CountryUS
Kind codeB2
Filing dateOct 1, 2021
Priority dateJun 18, 2021
Publication dateApr 1, 2025
Grant dateApr 1, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate, and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern. Portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer are removed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: forming a first resist layer over a substrate; forming a second resist layer over the first resist layer, wherein the second resist layer is a metal-containing resist; patterning the second resist layer to expose a portion of the first resist layer to form a second resist layer pattern, wherein the patterning includes exposing the second resist layer to a scanning electron beam; exposing the first resist layer to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern; and removing portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer. 2. The method according to claim 1 , wherein the exposing the first resist layer to diffracted XUV radiation includes a directional exposure. 3. The method according to claim 1 , wherein the second resist layer is made of a negative tone resist. 4. The method according to claim 1 , wherein the diffracted XUV radiation has a wavelength ranging from 0.1 nm to 100 nm. 5. The method according to claim 4 , wherein the diffracted XUV radiation has a wavelength ranging from 10 nm to 30 nm. 6. The method according to claim 1 , wherein the first resist layer is a chemically amplified resist. 7. The method according to claim 1 , wherein the second resist layer is formed directly on the first resist layer. 8. The method according to claim 1 , wherein the second resist layer comprises an organometallic compound. 9. The method according to claim 1 , wherein the second resist layer comprises a tin oxide. 10. A method of manufacturing a semiconductor device, comprising, forming a first photoresist layer over a substrate; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer is different from the first photoresist layer, and the second photoresist layer is a metal-containing resist; selectively exposing the second photoresist layer to a scanning electron beam to form a latent image in the second photoresist layer; developing the second photoresist layer to form a pattern in the second photoresist layer exposing a portion of the first photoresist layer; flood exposing remaining portions of the second photoresist layer and the first photoresist layer to an exposure radiation having a wavelength ranging from 0.1 nm to 100 nm, wherein the remaining portions of the second photoresist layer diffract the exposure radiation; and developing the first photoresist layer to expose portions of the substrate. 11. The method according to claim 10 , wherein the flood exposing is a directional exposure. 12. The method according to claim 10 , wherein the first photoresist layer is made of a positive tone resist and the second photoresist layer is a made of a negative tone resist. 13. The method according to claim 10 , wherein the first photoresist layer is a chemically amplified resist. 14. The method according to claim 10 , wherein the second resist layer is formed directly on the first resist layer. 15. The method according to claim 10 , wherein the remaining second photoresist layer is removed during the developing the first photoresist layer. 16. A method of manufacturing a semiconductor device, comprising: forming a first resist layer over a substrate; forming a second resist layer over the first resist layer, wherein the second resist layer is a metal-containing resist; exposing the second resist layer to a scanning electron beam; developing the second resist layer to form a second resist layer pattern in the second resist layer exposing a portion of the first resist layer; exposing the first resist layer to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern; and removing portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer. 17. The method according to claim 16 , wherein the exposing the first resist layer to diffracted XUV radiation includes a directional exposure. 18. The method according to claim 16 , wherein the second resist layer is a made of a negative tone resist. 19. The method according to claim 16 , wherein the diffracted XUV radiation has a wavelength ranging from 0.1 nm to 100 nm. 20. The method according to claim 19 , wherein the diffracted XUV radiation has a wavelength ranging from 10 nm to 30 nm.

Assignees

Inventors

Classifications

  • Photolithographic processes · CPC title

  • using masks for insulating materials · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • using lasers · CPC title

  • in the presence of a plasma [PECVD] · CPC title

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What does patent US12265332B2 cover?
A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate, and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist la…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/2041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).