Stacked planar field effect transistors with 2D material channels

Patent metadata

Field	Value
Publication number	US-12249643-B2
Application number	US-202117482940-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

First claim

What is claimed is:

1. A stacked device, comprising:
a plurality of dielectric support bridges on a substrate;
a first two-dimensional (2D) channel layer on a first side of each of the plurality of dielectric support bridges;
a gate dielectric sheet on the first two-dimensional (2D) channel layer;
a second two-dimensional (2D) channel layer having a vertical rippled profile that conforms on a second side of the first two-dimensional (2D) channel layer, the vertical rippled profile following an uneven surface on the plurality of dielectric support bridges; and
a second gate dielectric layer on the gate dielectric sheet.

2. The stacked device of claim 1 , wherein the first two-dimensional (2D) channel layer wraps around four sides of each of the plurality of dielectric support bridges.

3. The stacked device of claim 1 , wherein there is a pair of gate dielectric sheets on each of the plurality of dielectric support bridges.

4. The stacked device of claim 1 , wherein the plurality of dielectric support bridges are made of silicon oxide (SiO).

5. The stacked device of claim 1 , further comprising a source/drain material fill on the second two-dimensional (2D) channel layer.

6. The stacked device of claim 5 , further comprising a first source/drain material layer between the source/drain material fill and the second two-dimensional (2D) channel layer.

7. The stacked device of claim 6 , further comprising a bottom dielectric layer between the substrate and the plurality of dielectric support bridges.

8. The stacked device of claim 7 , further comprising an active gate structure between one or more pairs of gate dielectric sheets.

9. The stacked device of claim 8 , further comprising further comprising an inner spacer on opposite sides of each of the active gate structures.

10. A stacked device, comprising:
a bottom dielectric layer on a substrate;
a plurality of dielectric support bridges on the bottom dielectric layer;
a first two-dimensional (2D) channel layer on a first side of each of the plurality of dielectric support bridges and on the bottom dielectric layer;
a gate dielectric sheet on a second side of the first two-dimensional (2D) channel layer;
a second two-dimensional (2D) channel layer having a vertical rippled profile that conforms on the first two-dimensional (2D) channel layer, the vertical rippled profile following an uneven surface on the plurality of dielectric support bridges; and
a second gate dielectric layer on the gate dielectric sheet.

11. The stacked device of claim 10 , wherein the first two-dimensional (2D) channel layer is a material selected from the group consisting of indium tin oxide (ITO), indium-aluminum-zinc-oxide (IAZO), molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), tungsten disulfide (WS 2 ), and tungsten diselenide (WSe 2 ).

12. The stacked device of claim 11 , wherein the second two-dimensional (2D) channel layer is a material selected from the group consisting of indium tin oxide (ITO), indium-aluminum-zinc-oxide (IAZO), molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), tungsten disulfide (WS 2 ), and tungsten diselenide (WSe 2 ).

13. The stacked device of claim 12 , further comprising a first source/drain material layer on the second two-dimensional (2D) channel layer.

14. The stacked device of claim 13 , further comprising a source/drain material fill.

15. The stacked device of claim 14 , further comprising an active gate structure between one or more pairs of gate dielectric sheets.

16. The stacked device of claim 15 , wherein the first source/drain material layer is a material selected from the group consisting of bismuth (Bi) and antimony (Sb).

17. The stacked device of claim 16 , wherein the source/drain material fill is a conductive material selected from the group consisting of aluminum (Al), tungsten (W), cobalt (Co), molybdenum (Mo), tantalum nitride (TaN), tantalum carbide (TaC), titanium nitride (TiN), titanium carbide (TiC), and combinations thereof.

18. A method of forming a stacked device, comprising:
forming one or more stacks of alternating sacrificial layers and bridging layers on a substrate;
removing the sacrificial layers to expose opposite sides of the bridging layers;
converting the bridging layers to dielectric support bridges;
forming a first two-dimensional (2D) channel layer on a first side of the exposed surfaces of the dielectric support bridges;
forming a first gate dielectric layer on the first two-dimensional (2D) channel layer;
forming disposable filler sections between the dielectric support bridges;
removing portions of the first gate dielectric layer on exposed sides of the first two-dimensional (2D) channel layer; and
forming a second two-dimensional (2D) channel layer within the portions along a second side of the first two-dimensional (2D) channel layer to form a vertical rippled profile.

19. The method of claim 18 , further comprising forming a first source/drain material layer are formed on the second two-dimensional (2D) channel layer.

20. The method of claim 19 , further comprising forming a source/drain material fill on the first source/drain material layer.

Assignees

• IBM

Inventors

• Gaul Andrew
• Frougier Julien
• Xie Ruilong
• Greene Andrew M
• Waskiewicz Christopher J

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title