Multi-channel gate-all-around FET

Patent metadata

Field	Value
Publication number	US-9748352-B2
Application number	US-201514984688-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Jun 23, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

First claim

The invention claimed is:

1. A method, comprising:
forming, on top of a substrate, a layered stack of SiGe layers alternating with silicon layers;
forming a temporary gate structure over the layered stack;
forming first and second insulating spacers that coat respective side walls of the temporary gate structure;
forming a source region below the temporary gate structure and adjacent to the first insulating spacer;
forming a drain region below the temporary gate structure and adjacent to the second insulating spacer;
forming from the layered stack an array of vertically stacked silicon nanowires, each nanowire having end portions and a central portion; and
replacing the temporary gate structure with a metal gate structure that fully surrounds the central portions of the nanowires to fill a volume of space between the nanowires, wherein forming the temporary gate structure includes:
forming a hard mask on top of the layered stack;
patterning the hard mask; and
removing the patterned hard mask adjacent to the insulating spacers, while retaining the patterned hard mask underneath the insulating spacers.

2. The method of claim 1 , further comprising forming an inter-layer dielectric (ILD) on top of the source and drain regions.

3. The method of claim 1 wherein forming the layered stack includes inserting SiGe into a silicon-on-insulator (SOI) substrate that includes a silicon layer on top of an insulating layer.

4. The method of claim 3 wherein inserting SiGe into a SOI substrate includes:
depositing SiGe on top of the silicon layer of the SOI substrate; and
forming a first SiGe layer between the silicon layer and the insulating layer by diffusing the SiGe through the silicon layer.

5. The method of claim 1 , wherein forming the array of vertically stacked silicon nanowires further comprises:
forming fins from the layered stack; and
removing lateral portions of at least two SiGe layers from the fins.

6. The method of claim 1 , further comprising rounding the silicon nanowires using a high-temperature H 2 silicon reflow process to form circular cylinders.

7. The method of claim 1 , further comprising forming a high-k gate oxide in contact with the silicon nanowires prior to replacing the temporary gate structure with the metal gate structure.

8. The method of claim 1 , further comprising:
first and second undercut regions by etching lateral portions of the SiGe layer, the first and second undercut regions being at the first and second sides of the etched stack, respectively, the method further comprising:
forming third and fourth insulating spacers in the first and second undercut regions, respectively, the third and fourth insulating spacers insulating the metal gate electrode from the source and drain regions.

9. A method, comprising:
forming a layered stack of alternating silicon and SiGe films;
forming a temporary gate structure including sidewall spacers and a temporary gate electrode;
forming a fin from the layered stack using the temporary gate structure as a mask;
forming undercut regions in the fin by etching the SiGe films laterally under the temporary gate structure;
filling the undercut regions with an insulating material;
removing the temporary gate electrode;
removing the SiGe films; and
replacing the temporary gate electrode and the SiGe films with a metal gate electrode, wherein forming the temporary gate structure includes:
forming a hard mask on top of the layered stack;
patterning the hard mask; and
removing the patterned hard mask adjacent to the sidewall spacers, while retaining the patterned hard mask underneath the sidewall spacers.

10. The method of claim 9 wherein the sidewall spacers have a spacer width, the undercut regions have an undercut depth, and the undercut depth approximately matches the spacer width.

11. The method of claim 9 further comprising forming a source region and a drain region that are spaced apart from the metal gate electrode by the insulating material.

12. The method of claim 9 , wherein replacing the temporary gate electrode and the SiGe film layers with a metal gate electrode includes:
removing a central portion of the hard mask using the sidewall spacers as a mask, while retaining portions of the hard mask underneath the sidewall spacers; and
depositing the metal gate electrode in an opening between the sidewall spacers and between the portions of the hard mask underneath the sidewall spacers.

13. The method of claim 9 , wherein forming the layered stack includes inserting SiGe into a silicon-on-insulator (SOI) substrate that includes a silicon layer on top of an insulating layer, wherein inserting SiGe into a SOI substrate includes:
depositing SiGe on top of the silicon layer of the SOI substrate; and
forming a first SiGe layer between the silicon layer and the insulating layer by diffusing the SiGe through the silicon layer.

14. A method, comprising:
forming, on top of a substrate, a layered stack of SiGe layers alternating with silicon layers;
forming a hard mask on top of the layered stack, the hard mask including a plurality of elongated strips;
forming a temporary gate structure over the hard mask and the layered stack;
forming a spacer layer on top and lateral sides of the temporary gate structure and on the hard mask;
etching the hard mask while using the spacer layer as a mask to form etched strips of the hard mask;
etching through the layered stack using the etched strips of the hard mask and the spacer layer as a mask to form an etched stack of the SiGe layers alternating with silicon layers;
forming a source region at a first side of the etched stack;
forming a drain region at a second side of the etched stack;
forming from the etched stack an array of vertically stacked silicon nanowires by etching through the etched stack using the etched strips of the hard mask as a mask, each nanowire having end portions and a central portion; and
replacing the temporary gate structure with a metal gate structure that fully surrounds the central portions of the nanowires to fill a volume of space between the nanowires.

15. The method of claim 14 , wherein:
etching through the layered stack to form the etched stack includes forming undercut regions in the etched stack by etching the SiGe films laterally and under the temporary gate structure; and
the sidewall spacers have a spacer width, the undercut regions have an undercut depth, and the undercut depth approximately matches the spacer width.

16. The method of claim 14 , wherein etching through the layered stack to form the etched stack includes forming first and second undercut regions in the etched stack by laterally etching the SiGe films, the first and second undercut regions being at the first and second sides of the etched stack, respectively, the method further comprising:
forming first and second insulating spacers in the first and second undercut regions, respectively, the first and second insulating spacers insulating the metal gate electrode from the source and drain regions.

17. The method of claim 14 , further comprising:
removing a portion of the spacer layer from the top side of the temporary gate structure, thereby leave side portions of the spacer layer as insulating spacers; and
removing a central portion of the hard mask using the insulating spacers as a mask, while retaining portions of the hard mask underneath the insulating spacers.

18. The method of claim 17 , further comprising forming an inter-layer dielectric on top of the source and drain regions and in conta

Assignees

• St Microelectronics Inc
• Globalfoundries Inc
• IBM
• St Microelectronics Inc

Inventors

• Liu Qing
• Xie Ruilong
• Yeh Chun-Chen
• Cai Xiuyu

Classifications

• H01L29/51

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic