Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width

Patent metadata

Field	Value
Publication number	US-9490323-B2
Application number	US-201514722402-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	Jun 13, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

First claim

What is claimed is:

1. A device comprising a field effect transistor (FET), the FET comprising:
a substrate;
a first channel pattern on the substrate, the first channel pattern comprising a first plurality of nanosheets arranged in a first horizontal plane that is parallel to a surface of the substrate, the first plurality of nanosheets spaced apart from each other in a first direction that is parallel to the surface of the substrate at a horizontal spacing distance between adjacent ones of the first plurality of nanosheets;
a second channel pattern on the first channel pattern and spaced apart from the first channel pattern in a second direction that is perpendicular to the surface of the substrate at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance, the second channel pattern comprising a second plurality of nanosheets arranged in a second horizontal plane that is parallel to the surface of the substrate, the second plurality of nanosheets spaced apart from each other in the first direction at the horizontal spacing distance between adjacent ones of the second plurality of nanosheets;
a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern; and
source/drain regions on opposing ends of the first channel pattern and second channel pattern, ones of the source/drain regions connected to a respective end of the first channel pattern and a respective corresponding end of the second channel pattern,
wherein the gate comprises a gate dielectric material that is configured to surround portions of ones of the first plurality of nanosheets and portions of ones of the second plurality of nanosheets,
wherein the gate comprises a work function tuning metal layer that is configured to surround portions of the gate dielectric material, the work function tuning metal layer being configured to control a work function of the FET, the work function tuning metal comprising a first continuous perimeter that surrounds four sides of the first channel pattern and a second continuous perimeter that surrounds four sides of the second channel pattern, and
wherein the gate comprises a low resistance gate metal layer on the work function tuning metal layer that surrounds the first and second continuous perimeters of the work function tuning metal and is between the first and second continuous perimeters of the work function tuning metal.

2. The device of claim 1 , wherein ones of the first plurality of nanosheets and ones of the second plurality of nanosheets comprise a ratio of width in the first direction to height in the second direction of at least 1:1.

3. The device of claim 2 , wherein ones of the first plurality of nanosheets and ones of the second plurality of nanosheets comprise a ratio of width in the first direction to height in the second direction of at least 2:1.

4. The device of claim 1 , wherein ones of the first plurality of nanosheets and ones of the second plurality of nanosheets comprise a height in the second direction in a range of about 2 nm to about 8 nm.

5. The device of claim 4 , wherein ones of the first plurality of nanosheets and ones of the second plurality of nanosheets comprise a height in the second direction in a range of about 3 nm to about 6 nm.

6. The device of claim 1 ,
wherein the work function tuning metal layer extends substantially continuously between adjacent ones of the first plurality of nanosheets and extends substantially continuously between adjacent ones of the second plurality of nanosheets,
wherein the first channel pattern comprises at least three nanosheets, and
wherein the second channel pattern comprises at least three nanosheets.

7. The device of claim 1 , wherein the FET is an n-type FET, the device further comprising a p-type FET, the p-type FET comprising:
a third channel pattern on the substrate, the third channel pattern comprising a third plurality of nanosheets spaced apart from each other at a second horizontal spacing distance between adjacent ones of the first plurality of nanosheets; and
a fourth channel pattern on the third channel pattern and spaced apart from the third channel pattern in the second direction at a second vertical spacing distance from the third channel pattern to the fourth channel pattern that is greater than the second horizontal spacing distance, the fourth channel pattern comprising a fourth plurality of nanosheets spaced apart from each other at the second horizontal spacing distance between adjacent ones of the fourth plurality of nanosheets,
wherein the nanosheets of the first through fourth channel patterns comprise Si, SiGe, Ge, or a group III-V semiconductor material,
wherein top and bottom surfaces of the nanosheets of the first channel pattern and second channel pattern comprise a first surface orientation, and
wherein top and bottom surfaces of the nanosheets of the third channel pattern and the fourth channel pattern comprise a second surface orientation.

8. The device of claim 7 , wherein the first surface orientation is the same as the second surface orientation.

9. The device of claim 8 , wherein the first surface orientation and second surface orientation are (110).

10. The device of claim 7 , wherein the first surface orientation is different from the second surface orientation.

11. The device of claim 10 , wherein the first surface orientation is (100) or (111) and the second surface orientation is (110).

12. A device comprising a field effect transistor (FET), the FET comprising:
a substrate;
a first channel pattern on the substrate, the first channel pattern comprising a first plurality of nanosheets arranged in a first horizontal plane that is parallel to a surface of the substrate, the first plurality of nanosheets spaced apart from each other in a first direction that is parallel to the surface of the substrate at a horizontal spacing distance between adjacent ones of the first plurality of nanosheets;
a second channel pattern on the first channel pattern and spaced apart from the first channel pattern in a second direction that is perpendicular to the surface of the substrate at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance, the second channel pattern comprising a second plurality of nanosheets arranged in a second horizontal plane that is parallel to the surface of the substrate, the second plurality of nanosheets spaced apart from each other in the first direction at the horizontal spacing distance between adjacent ones of the second plurality of nanosheets;
a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern; and
source/drain regions on opposing ends of the first channel pattern and second channel pattern, ones of the source/drain regions connected to a respective end of the first channel pattern and a respective corresponding end of the second channel pattern,
wherein the gate comprises:
a gate dielectric material that is configured to surround portions of ones of the first plurality of nanosheets and portions of ones of the second plurality of nanosheets; and
a low resistance gate metal layer on the gate dielectric material that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and

wherein the gate dielectric material extends substantially continuously between adjacent ones of the first plurality of nanosheets and extends substantially continuously between adjacent ones of the second plurality of na

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rodder Mark S
• Obradovic Borna J
• Sengupta Rwik

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title