Stacked graphene field-effect transistor

US9508801B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9508801-B2
Application numberUS-201514591988-A
CountryUS
Kind codeB2
Filing dateJan 8, 2015
Priority dateJan 8, 2015
Publication dateNov 29, 2016
Grant dateNov 29, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A graphene field-effect transistor (GFET) structure comprising: a semiconductor substrate that has a dielectric coating; a layer of metal overlaying the semiconductor substrate; a first layer of gate dielectric overlaying the layer of metal; a patterned layer of graphene overlaying a portion of the first layer of gate dielectric; a second layer of gate dielectric overlaying the patterned layer of graphene; a top layer of metal overlaying a topmost layer of gate dielectric; a layer of dielectric overlaying the top layer of metal; a source contact and a drain contact self-aligned to the graphene layer, wherein the graphene layer is edge-contacted to the source and drain contacts; and wherein outer surfaces of the metal layers are oxidized. 2. The GFET structure of claim 1 , wherein the layer of metal and the top layer of metal comprise Aluminum; and wherein the source contact and the drain contact comprise Chromium. 3. The GFET structure of claim 1 , further comprising: a second layer of metal overlaying the second layer of gate dielectric; a third layer of gate dielectric overlaying the second layer of metal; a second patterned layer of graphene overlaying a portion of the third layer of gate dielectric; and a fourth layer of gate dielectric overlaying the second patterned layer of graphene. 4. A graphene field-effect transistor (GFET) structure comprising: a GFET structure on a semiconductor substrate, wherein: the GFET structure includes a wider portion, wherein the wider portion comprises: a layer of metal overlaying the semiconductor substrate; a layer of gate dielectric overlaying the layer of metal; a top layer of metal overlaying a topmost layer of gate dielectric; a layer of dielectric overlaying the top layer of metal, wherein outer surfaces of the metal layers are oxidized; and the GFET structure includes a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers. 5. The GFET structure of claim 4 , wherein the narrow extension portion comprises: a layer of metal overlaying the semiconductor substrate; a first layer of gate dielectric overlaying the layer of metal; a patterned layer of graphene overlaying a portion of the first layer of gate dielectric; a second layer of gate dielectric overlaying the patterned layer of graphene; a top layer of metal overlaying a topmost layer of gate dielectric; a layer of dielectric overlaying the top layer of metal; a source contact and a drain contact self-aligned to the graphene layer, wherein the graphene layer is edge-contacted to the source and drain contacts; and wherein outer surfaces of the metal layers are oxidized. 6. The GFET structure of claim 4 , wherein the wider portion further comprises: a through hole via in the wider portion; and a gate metal plug filling the through hole via in the wider portion. 7. The GFET structure of claim 5 , wherein the layer of metal and the top layer of metal comprise Aluminum; and wherein the source contact and the drain contact comprise Chromium.

Assignees

Inventors

Classifications

  • Etching of wafers, substrates or parts of devices · CPC title

  • of a metallic layer · CPC title

  • Carbon, e.g. diamond-like carbon · CPC title

  • the semiconductor being diamond, semiconducting diamond-like carbon or graphene · CPC title

  • to diamond, semiconducting diamond-like carbon or graphene · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9508801B2 cover?
In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D30/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).