Selective patterning of vias with hardmasks

Patent metadata

Field	Value
Publication number	US-12243771-B2
Application number	US-202217666767-A
Country	US
Kind code	B2
Filing date	Feb 8, 2022
Priority date	Sep 13, 2019
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first metal line having a planar upper surface across its width colinearly disposed relative to a second metal structure in a same layer, wherein the first metal line includes a single line end that a subtractively etched self-aligned via is positioned on adjacent to a line cut region, wherein the subtractively etched self-aligned via is etched from the first metal line and the subtractively etched self-aligned via and the first metal line share a vertical boundary at an end portion of the first metal line facing towards the second metal structure.

2. The semiconductor structure of claim 1 , wherein the single line end includes no line end critical dimension variation based on self-aligning of the subtractively etched self-aligned via.

3. The semiconductor structure of claim 1 , wherein a via critical dimension at the single line end is controlled by a spacer thickness.

4. The semiconductor structure of claim 1 , wherein the subtractively etched self-aligned via is directly at the single line end.

5. The semiconductor structure of claim 1 , wherein the subtractively etched self-aligned via is directly on an upper surface of the first metal line.

6. The semiconductor structure of claim 1 , wherein a composition of the first metal line is different from a composition of the subtractively etched self-aligned via.

7. The semiconductor structure of claim 1 , wherein the first metal line and the second metal structure are present in a line level further comprising a line level dielectric.

8. The semiconductor structure of claim 7 , wherein the subtractively etched self-aligned via is present in a via level further comprising a via level dielectric.

9. The semiconductor structure of claim 8 , wherein the via level dielectric has a different composition than the line level dielectric.

10. A semiconductor structure, comprising:
a first metal line having a planar upper surface across its width colinearly disposed relative to a second metal structure in a same layer; and
a subtractively etched self-aligned top via positioned on a single line end of the planar upper surface of the first metal line, wherein the single line end is formed adjacent to a line cut region, and the subtractively etched self-aligned top via is positioned on the single line end of the first metal line contacting a top surface of the first metal line, wherein the subtractively etched self-aligned top via is etched from the first metal line and the subtractively etched self-aligned top via and the first metal line and share a vertical boundary at the single line end facing towards of the second metal structure.

11. The semiconductor structure of claim 10 , wherein the single line end includes no line end critical dimension variation based on self-aligning of the subtractively etched self-aligned top via.

12. The semiconductor structure of claim 10 , wherein a via critical dimension at the single line end is controlled by a spacer thickness.

13. The semiconductor structure of claim 10 , wherein a composition of the first metal line is different from a composition of the subtractively etched self-aligned top via.

14. The semiconductor structure of claim 13 , wherein the first metal line and the second metal structure are present in a line level further comprising a line level dielectric.

15. The semiconductor structure of claim 14 , wherein the subtractively etched self-aligned top via is present in a via level further comprising a via level dielectric.

16. The semiconductor structure of claim 15 , wherein the via level dielectric has a different composition than the line level dielectric.

17. A semiconductor structure, comprising:
a line level including a line level dielectric having a first metal line having a planar upper surface across its width colinearly disposed relative to a second metal structure; and
a via level atop the line level including a subtractively etched self-aligned top via positioned on a single line end of the planar upper surface of the first metal line, wherein the single line end is formed adjacent to a line cut region, wherein the subtractively etched self-aligned top via is etched from the first metal line and the subtractively etched self-aligned via and the first metal line share a vertical boundary at an end portion of the first metal line facing towards the second metal structure.

18. The semiconductor structure of claim 17 , wherein at least one line end includes no line end critical dimension variation based on self-aligning of the subtractively etched self-aligned top via.

19. The semiconductor structure of claim 17 , wherein a via critical dimension at the single line end is controlled by a spacer thickness.

Assignees

• IBM
• Interational Business Machines Corp

Inventors

• Arnold John C
• Dutta Ashim
• Metzler Dominik
• Philip Timothy M
• Mukesh Sagarika

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title