Strain detection structures for bonded wafers and chips

Patent metadata

Field	Value
Publication number	US-2016118348-A1
Application number	US-201414522083-A
Country	US
Kind code	A1
Filing date	Oct 23, 2014
Priority date	Oct 23, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

First claim

What is claimed:

1 . A method, comprising:
forming lower metal wiring structures associated with a lower wafer structure; bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer; forming upper metal wiring structures; electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures; and forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

2 . The method of claim 1 , wherein the bonding of the lower wafer structure to the upper wafer structure is an oxide bonding process.

3 . The method of claim 1 , wherein the formation of through silicon via structures comprises an etching and deposition process, connecting the lower metal wiring structures to the upper metal wiring structures.

4 . The method of claim 3 , wherein the deposition process is a liner deposition process followed by an electroplating process of copper.

5 . The method of claim 1 , wherein the bonding process comprises bonding at least one additional wafer between the lower wafer and the upper wafer.

6 . The method of claim 5 , further comprising forming additional chains of metal structures on different levels of a multistacked structure comprising at least the lower wafer structure, the upper wafer structure and the at least one additional wafer bonded together with intervening insulator layers to form either a resistance strain gauge or a capacitance strain gauge electrically isolated from active devices.

7 . The method of claim 1 , further comprising forming via structures interleaved with the through silicon via structures to form capacitance strain gauges.

8 . The method of claim 7 , wherein the via structures interleaved with the through silicon via structures are formed on a wafer structure below the lower wafer structure.

9 . The method of claim 8 , wherein the via structures extend into the lower wafer structure.

10 . The method of claim 1 , wherein the metal wiring structures associated with the lower wafer structure, the upper metal wiring structures and the through silicon via structures are formed in a kef area.

11 . The method of claim 10 , wherein the metal wiring structures of the lower wafer, the upper metal wiring structures and the through silicon via structures form at least two strain gauges concentrically formed in a pattern on different layers.

12 . A method, comprising:
bonding together multiple wafer structures; and forming a metal structure which is isolated from active devices, and which extends between multiple layers of the multiple wafer structures to measure either resistance or capacitance.

13 . The method of claim 12 , wherein the forming the metal structure comprising forming a first wiring layer associated with a first wafer structure and a second wiring layer associated with a second wafer structure, and electrically linking together the first wiring layer and the second wiring layer by form a through silicon via extending between the first wiring layer and the second wiring layer.

14 . The method of claim 13 , wherein the multiple wafer structures comprise at least three wafer structures.

15 . The method of claim 13 , wherein the formation of the through silicon via extends through at least one of the multiple wafer structures and is formed by lining a via with a first metal material and then filling the via with additional metal material by an electroplating process.

16 . The method of claim 12 , wherein the metal structure comprising an upper metal structure and a lower metal structure which are not in contact with one another, and which includes forming an interleaved via structures that overlap with one another.

17 . The method of claim 16 , wherein the upper metal structure comprising a linked metal structure extending at least through one of wafer structure of the multiple wafer structures.

18 . A device comprising:
a first metal structure extending between multiple wafer structures, which respond eclectically to thermal and strain energies in a three axial plane; and a connecting structure connecting the first structure to an outside environment.

19 . The device of claim 18 , further comprising a second metal structure interleaved with the first metal structure, wherein a combination of the first metal structure and the second metal structure measure a capacitance in response to the thermal and strain energies in the three axial plane.

20 . The device of claim 18 , wherein the first metal structure comprising upper wiring structures and lower wiring structure, connected together by via structures extending between the multiple wafer structures.

Assignees

• IBM

Inventors

• Farooq Mukta G
• Fitzsimmons John A
• Kaltalioglu Erdem
• Lin Wei
• Skordas Spyridon
• Winstel Kevin R

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title