Self aligned via in integrated circuit

Patent metadata

Field	Value
Publication number	US-2016379929-A1
Application number	US-201615152981-A
Country	US
Kind code	A1
Filing date	May 12, 2016
Priority date	Jun 24, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

First claim

What is claimed is:

1 . A method for forming a via in an integrated circuit, the method comprising:
patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer; removing an exposed portion of the first OPL layer to define a cavity; removing an exposed portion of a second hardmask in the cavity; removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity; removing an exposed portion of a first cap layer in the cavity; removing an exposed portion of a second dielectric layer to further define the cavity; removing an exposed portion of a second cap layer to further define the cavity; removing an exposed portion of a liner layer over a second conductive material in the cavity; and depositing a conductive material in the cavity.

2 . The method of claim 1 , further comprising depositing a single layer of liner material in the cavity prior to depositing a conductive material in the cavity.

3 . The method of claim 1 , wherein the first hardmask includes a titanium nitride (TiN) layer and an oxide material layer disposed between the TiN layer and the first OPL layer.

4 . The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (ME) process that is selective to TiN material.

5 . The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (ME) process that is selective to TiN and oxide materials.

6 . The method of claim 1 , wherein the second hardmask includes an oxide material.

7 . The method of claim 1 , wherein the second hardmask includes a nitride material.

8 . An integrated circuit comprising:
a first dielectric layer; a first interconnect arranged in the first dielectric layer, the first interconnect including a conductive material; a second dielectric layer arranged on the first dielectric layer; a second interconnect arranged in the second dielectric layer, the second interconnect including a conductive material; a third dielectric layer arranged on the second dielectric layer; a cavity partially defined by the conductive material of the first interconnect, the second dielectric layer, and the third dielectric layer; a single liner layer disposed in the cavity over the conductive material of the first interconnect; and a conductive material disposed on the single liner layer in the cavity, wherein the conductive material disposed on the single liner layer in the cavity partially defines a conductive via that passes through the third dielectric layer and the second dielectric layer.

9 . The circuit of claim 8 , further comprising a first insulator layer disposed between the first interconnect and the second dielectric layer, the insulator layer further defining the cavity.

10 . The circuit of claim 8 , further comprising a second insulator layer disposed between the second interconnect and the third dielectric layer, the insulator layer further defining the cavity.

11 . The circuit of claim 8 , further comprising:
a second cavity partially defined by the conductive material of the second interconnect and the third dielectric layer; a single liner layer disposed in the second cavity over the conductive material of the first interconnect; and a conductive material disposed on the single liner layer in the second cavity, wherein the conductive material disposed on the single liner layer in the second cavity partially defines a conductive via that passes through the third dielectric layer.

12 . The circuit of claim 8 , further comprising:
a third interconnect arranged in the second dielectric layer; a conductive material arranged in the second dielectric layer, the conducive material contacting the third interconnect and the first interconnect.

Assignees

• IBM
• Tokyo Electron Ltd
• St Microelectronics Inc

Inventors

• Feurprier Yannick
• Lee Joe
• Liebmann Lars W
• Mignot Yann
• Spooner Terry A
• Trickett Douglas M
• Yilmaz Mehmet

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/287

  by chemical means · CPC title