Semiconductor device having a contact structure

Patent metadata

Field	Value
Publication number	US-12237261-B2
Application number	US-202318312181-A
Country	US
Kind code	B2
Filing date	May 4, 2023
Priority date	Feb 26, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening;
a via in the via opening; and
a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and
a conductive fill, wherein the first liner layer surrounds the conductive fill.

2. The semiconductor device of claim 1 , wherein a third thickness of the conductive fill over the via is greater than a fourth thickness of the conductive fill over the insulating layer.

3. The semiconductor device of claim 1 , wherein the conductive line further comprises a second liner layer, and the second liner layer is between the conductive fill and the first liner layer.

4. The semiconductor device of claim 3 , wherein the second liner layer is over a top-most surface of the conductive fill.

5. The semiconductor device of claim 1 , wherein the conductive line further comprises a second liner layer, and the first liner layer is between the conductive fill and the second liner layer.

6. The semiconductor device of claim 5 , wherein the second liner layer directly contacts the via.

7. The semiconductor device of claim 5 , wherein a bottommost surface of the second liner layer is coplanar with a bottommost surface of the via.

8. The semiconductor device of claim 1 , wherein the via directly contacts the insulating layer.

9. A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening;
a via in the via opening, wherein the via comprises a first conductive material; and
a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer having a variable thickness, wherein thickness is measured in a direction perpendicular to a top surface of the insulating layer,
a second liner layer over the first liner layer, and
a conductive fill comprising a second conductive material, wherein the first liner layer, in the direction perpendicular to the top surface of the insulating layer, is between a portion of the insulating layer and the conductive fill.

10. The semiconductor device of claim 9 , wherein the first conductive material is a same material as the second conductive material.

11. The semiconductor device of claim 9 , wherein the via is continuous with the conductive fill.

12. The semiconductor device of claim 9 , wherein the first liner layer is between the via and the insulating layer.

13. The semiconductor device of claim 9 , wherein a bottommost surface of the first liner layer is below a bottommost surface of the via.

14. The semiconductor device of claim 9 , wherein a thickness of the second liner layer is variable.

15. The semiconductor device of claim 9 , wherein the first liner layer is between the conductive fill and the via.

16. A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening;
a via in the via opening, wherein the via comprises a first conductive material; and
a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer having a variable thickness, wherein a portion of the first liner layer over the insulating layer has a uniform thickness, and
a conductive fill.

17. The semiconductor device of claim 16 , wherein the first liner layer is between the via and the conductive fill.

18. The semiconductor device of claim 16 , wherein the via has a tapered profile.

19. The semiconductor device of claim 16 , wherein the conductive line comprises a second liner layer directly contacting the via.

20. The semiconductor device of claim 19 , wherein the first liner layer is between the second liner layer and a sidewall of the conductive fill.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Liu Yao-Min
• Su Hung-Wen
• Chi Chih-Chien
• Lin Chi-Feng

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title