SRAM with two-level voltage regulator

Patent metadata

Field	Value
Publication number	US-9286952-B2
Application number	US-201414320074-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A programmable logic device (PLD) is provided with a two-level voltage regulator for powering SRAM cells within the device. In one example, a PLD includes a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device. The PLD also includes a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage. The SRAM cells are powered through a coupling to the first power supply node. The PLD also includes a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.

First claim

I claim:

1. A programmable logic device, comprising:
a plurality of static random access memory (SRAM) cells arranged into a plurality of rows;
a plurality of word lines corresponding to the plurality of rows, wherein each SRAM cell comprises a pair of access transistors having their gates coupled to the SRAM cell's row's word line;
a plurality of word line drivers corresponding to the plurality of word lines, each word line driver being powered through a coupling to a second power supply node;
a switch coupled between the first power supply node and the second power supply node, wherein the control circuit is configured to close the switch during a write operation so that a selected one of the word lines is charged to the reduced voltage and to open the switch during a read operation;

a two-level voltage regulator configured to selectively charge a first power supply node to one of a reduced voltage and an enhanced voltage that is greater than the reduced voltage, wherein the SRAM cells are powered through a coupling to the first power supply node;
a power regulator configured to charge the second power supply node to an operating voltage that is lower than the reduced voltage during the read operation so that a selected one of the word lines is charged to the operating voltage during the read operation; and
a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during the write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.

2. The programmable logic device of claim 1 , wherein the control circuit is further configured to control the two-level voltage regulator to charge the first power supply voltage to the enhanced level during a read operation for the SRAM cells.

3. A programmable logic device, comprising:
a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device;
a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage, wherein the SRAM cells are powered through a coupling to the first power supply node; and
a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device

wherein the first power supply node comprises a voltage rail, and wherein the two-level voltage regulator comprises a differential amplifier configured to drive a gate of a transistor coupled between a second power supply node and the voltage rail responsive to a difference between a feedback voltage and a reference voltage.

4. The programmable logic device of claim 3 , wherein the SRAM cells are arranged into a plurality of rows, the programmable logic device further comprising:
a plurality of word lines corresponding to the plurality of rows, wherein each SRAM cell comprises a pair of access transistors having their gates coupled to the SRAM cell's row's word line;
a first switch configured to be closed by the control circuit during a read operation and opened by the control circuit during a write operation;
a second switch configured to be opened by the control circuit during the read operation and closed by the control circuit during the write operation; and
a plurality of word line drivers corresponding to the plurality of word lines, each word line driver being selectively powered by the first power supply node through the first switch or by a second power supply node through the second switch.

5. The programmable logic device of claim 3 , wherein the SRAM cells are arranged into a plurality of rows, the programmable logic device further comprising:
a plurality of word lines corresponding to the plurality of rows, wherein each SRAM cell comprises a pair of access transistors having their gates coupled to the SRAM cell's row's word line;
a plurality of word line drivers corresponding to the plurality of word lines, each word line driver being powered through a coupling to a second power supply node; and
a switch coupled between the first power supply node and the second power supply node, wherein the control circuit is configured to close the switch during the write operation so that a selected one of the word lines is charged to the reduced voltage and to open the switch during the read operation.

6. The programmable logic device of claim 5 , further comprising a power regulator configured to charge the second power supply node to an operating voltage that is lower than the reduced voltage so that a selected one of the word lines is charged to the operating voltage during the read operation.

7. The programmable logic device of claim 3 , further comprising a bandgap reference circuit configured to provide the reference voltage.

8. The programmable logic device of claim 3 , further comprising;
a voltage divider coupled to the voltage rail, the voltage divider including a first node and a second node; and
a multiplexer configured to select between the first node and the second node to provide the feedback voltage to the differential amplifier.

9. The programmable logic device of claim 3 , wherein the coupled transistor comprises a thick-gate-oxide transistor.

10. The programmable logic device of claim 9 , wherein the thick-gate-oxide coupled transistor comprises a thick-gate-oxide NMOS transistor.

11. The programmable logic device of claim 7 , further comprising a shunt transistor coupled between ground and the voltage rail.

12. A method, comprising:
powering an SRAM cell within a programmable logic device with a reduced power supply voltage;
while the SRAM cell is powered by the reduced power supply voltage, writing to the SRAM cell to configure the programmable logic device by accessing the SRAM cell through an access transistor having its gate charged by the reduced power supply voltage; and
operating the configured programmable logic device while the SRAM cell is powered with an increased power supply voltage that is greater than the reduced power supply voltage; and
reading a stored value in the SRAM cell while the SRAM cell is powered with the increased power supply voltage, wherein reading the stored value in the SRAM cell occurs through the access transistor by charging the gate of the access transistor to an operating voltage (VCC) that is lower than the reduced power supply voltage.

13. The method of claim 12 , further comprising receiving a control signal, wherein the powering with a reduced power supply voltage is performed in response to an activation of the control signal, the method further comprising powering the SRAM cell with the increased power supply voltage in response to a deactivation of the control signal.

14. The method of claim 12 , wherein the reduced power supply voltage is greater than a voltage of logic blocks coupled to the SRAM cells.

15. A method, comprising:
powering an SRAM cell within a programmable logic device with a reduced power supply voltage;
while the SRAM cell is powered by the reduced power supply voltage, writing to the SRAM cell to configure the programmable logic device by accessing the SRAM cell through an access transistor having its gate charged by the reduced power supply voltage; and
operating the configured programmable logic device while

Assignees

• Lattice Semiconductor Corp

Inventors

• Mclaury Loren

Classifications

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title