Low power transient voltage collapse apparatus and method for a memory cell

Patent metadata

Field	Value
Publication number	US-9263121-B2
Application number	US-201313976403-A
Country	US
Kind code	B2
Filing date	May 16, 2013
Priority date	May 16, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

First claim

We claim:

1. An apparatus comprising:
a power supply node;
a device operable to adjust voltage on the power supply node;
a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node, wherein the feedback unit comprises a capacitor; and
a logic unit coupled to the feedback unit to generate a feedback control signal to control the feedback unit.

2. The apparatus of claim 1 , wherein the device is coupled to the power supply node and another node, and wherein the other node is at least one of:
a ground node;
a capacitive load; or
a node with a voltage potential lower than a power supply voltage.

3. The apparatus of claim 2 , wherein the device is at least one of:
a p-type device; or
an n-type device.

4. The apparatus of claim 1 , wherein the feedback unit comprises a circuit with hysteresis.

5. The apparatus of claim 4 , wherein the circuit with hysteresis comprises a Schmitt-trigger which includes a device which is operable to adjust tripping point of the Schmitt-trigger base on the feedback control signal.

6. The apparatus of claim 1 , wherein the capacitor is at least one of:
a metal capacitor;
a non-metal capacitor; or
a hybrid capacitor including a metal capacitor and a device capacitor.

7. The apparatus of claim 1 , wherein one terminal of the capacitor is connected to the power supply node, and wherein another terminal of the capacitor is operable to couple to a reference voltage or to a floating node.

8. The apparatus of claim 1 further comprises a memory cell coupled to the power supply node.

9. An apparatus comprising:
a power supply node;
an internal node operable to float or be driven by a reference signal;
a pull-down device operable to pull down voltage on the power supply node; and
a capacitor having a the first terminal connected to the power supply node and a second terminal connected to the internal node, the capacitor to indirectly control the pull-down device in response to a voltage level of the voltage on the power supply node.

10. The apparatus of claim 9 further comprises a logic gate coupled to the internal node and the pull-down device.

11. The apparatus of claim 9 further comprises:
a reference generator to generate the reference signal; and
a select unit to couple the reference signal to the internal node in response to a control signal.

12. The apparatus of claim 11 , wherein the select unit is a pass-gate.

13. The apparatus of claim 9 further comprises a memory cell coupled to the power supply node.

14. The apparatus of claim 9 , wherein the pull-down device is coupled to the power supply node and another node.

15. The apparatus of claim 14 , wherein the another node is at least one of:
a ground node;
a capacitive load; or
a node with a voltage potential lower than a power supply voltage.

16. The apparatus of claim 15 , wherein the pull-down device is at least one of:
a p-type device; or
an n-type device.

17. A system comprising:
a wireless interface;
a processor operable to communicate with another device using the wireless interface, the processor including:
a power supply node;
a device operable to adjust voltage on the power supply node;
a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node,

wherein the feedback unit comprises a capacitor; and
a logic unit coupled to the feedback unit to generate a feedback control signal to control the feedback unit; and

a display unit to display content processed by the processor.

18. The system of claim 17 , wherein the device is coupled to the power supply node and another node, and wherein the other node is at least one of:
a ground node;
a capacitive load; or
a node with a voltage potential lower than a power supply voltage.

19. The apparatus of claim 18 , wherein the device is at least one of:
a p-type device; or
an n-type device.

Assignees

• Karl Eric A
• Ng Yong-Gee
• Dray Cyrille
• Intel Corp

Inventors

• Karl Eric A
• Ng Yong-Gee
• Dray Cyrille

Classifications

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/414

  for memory cells of the bipolar type · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title