Dual-port SRAM with bit line clamping

Patent metadata

Field	Value
Publication number	US-8971146-B2
Application number	US-201313901853-A
Country	US
Kind code	B2
Filing date	May 24, 2013
Priority date	Aug 17, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.

First claim

We claim:

1. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a first stage clamping circuit operable to clamp the internal node to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the internal node during the write operation;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a second stage clamping circuit operable to clamp the plurality of bit lines to a clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line during the write operation.

2. The memory of claim 1 , wherein the memory comprises a dual-port memory.

3. The memory of claim 1 , wherein the second stage clamping circuit includes a plurality of clamping transistors corresponding to the plurality of bit lines.

4. The memory of claim 1 , wherein the memory comprises SRAM.

5. The memory of claim 1 , wherein the memory is embedded in a programmable logic device.

6. The memory of claim 5 , wherein the programmable logic device is a field programmable gate array.

7. The memory of claim 1 , wherein each bit line is one of a complementary bit line pair.

8. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a clamping circuit operable to clamp the plurality of bit lines to a clamping voltage, wherein the clamping circuit is further operable to unclamp the selected bit line driven by the write driver during the write operation.

9. The memory of claim 8 , wherein the memory comprises a dual-port memory.

10. The memory of claim 8 , wherein the clamping circuit includes a plurality of clamping transistors corresponding to the plurality of bit lines.

11. The memory of claim 8 , wherein each bit line is one of a complementary bit line pair.

12. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a clamping circuit operable to clamp the internal node to a clamping voltage, wherein the clamping circuit is further operable to unclamp the internal node during the write operation.

Assignees

• Lattice Semiconductor Corp

Inventors

• Sharpe-Geisler Brad
• Swensen Timothy Scott
• Tsai Sam
• Fontana Fabiano

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title