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US-2024233786-A9 · Jul 11, 2024 · US
Memory device and method of controlling leakage current within such a memory device
US9147451B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147451-B2 |
| Application number | US-201313847743-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 20, 2013 |
| Priority date | Mar 20, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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Abstract
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A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.
First claim
Opening claim text (preview).
We claim: 1. A memory device comprising: an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line, each column group having an active mode of operation where a read operation may be performed on an activated memory cell within the at least one column…
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Physics · mapped topic
- G11C7/18Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9147451B2 cover?
- A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level pri…
- Who is the assignee on this patent?
- Advanced Risc Mach Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C7/18. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).