Oxide-based resistive memory having a plasma-exposed bottom electrode

Patent metadata

Field	Value
Publication number	US-12225833-B2
Application number	US-202318164125-A
Country	US
Kind code	B2
Filing date	Feb 3, 2023
Priority date	Jun 11, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

First claim

What is claimed is:

1. A resistive switching device comprising:
a metal interconnect electrode; and
a charge-particle-treated memory stack over the metal interconnect electrode;
wherein the memory stack comprises a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode;
wherein the dielectric layer comprises a portion of a blanket dielectric layer;
wherein the bottom electrode comprises a portion of a blanket bottom electrode layer; and
wherein the charge-particle-treated memory stack further comprises a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

2. The device of claim 1 , wherein dimensions of the charge-particle-treated memory stack are larger than dimensions of the metal interconnect electrode.

3. The device of claim 2 , wherein the metal interconnect electrode is on a surface of a metal interconnect layer.

4. The device of claim 3 , the metal interconnect layer is formed in an inter-level dielectric over a substrate.

5. The device of claim 4 , wherein the memory stack comprises a filament-forming voltage characteristic determined based at least in part on the current-conducting filament characteristic.

6. The device of claim 1 , wherein the bottom electrode, the dielectric layer, and the top electrode define a Resistive Random Access Memory (RRAM) device memory stack.

7. The device of claim 2 further comprising a spacer on a sidewall of the top electrode.

8. The device of claim 6 , wherein the spacer is positioned on a surface of the dielectric layer such that an outer sidewall of the spacer is coplanar to a sidewall of the bottom electrode, and wherein the spacer is configured to encapsulate the top electrode to prevent a short between the top electrode and the bottom electrode.

9. The device of claim 7 further comprising a hard mask on a surface of the top electrode, the hard mask adjacent to an inner sidewall of the spacer, wherein the hard mask comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen.

10. The device of claim 1 , wherein:
the bottom electrode comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen;
the dielectric layer comprises hafnium oxide; and
the top electrode comprises titanium nitride.

11. A resistive switching device comprising:
a memory stack comprising a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode; and
a spacer on a sidewall of at least a portion of the memory stack;
wherein the dielectric layer comprises a portion of a blanket dielectric layer;
wherein the bottom electrode comprises a portion of a blanket bottom electrode layer;
wherein the dielectric layer comprises a current-conducting filament characteristic that results from a charge particle treatment applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed; and
wherein the spacer prevents a short between the top electrode and the bottom electrode.

12. The device of claim 11 , wherein dimensions of the charge-particle-treated memory stack are larger than dimensions of the metal interconnect electrode.

13. The device of claim 12 , wherein the metal interconnect electrode is on a surface of a metal interconnect layer.

14. The device of claim 13 , the metal interconnect layer is formed in an inter-level dielectric over a substrate.

15. The device of claim 14 , wherein the charge-particle-treated memory stack comprises a filament-forming voltage characteristic determined based at least in part on the current-conducting filament characteristic.

16. The device of claim 11 , wherein the bottom electrode, the dielectric layer, and the top electrode define a Resistive Random Access Memory (RRAM) device memory stack.

17. The device of claim 12 , wherein the portion of the memory stack comprises a sidewall of the top electrode.

18. The device of claim 17 , wherein the spacer is positioned on a surface of the dielectric layer such that an outer sidewall of the spacer is coplanar to a sidewall of the bottom electrode, and wherein the spacer is configured to encapsulate the top electrode to prevent a short between the top electrode and the bottom electrode.

19. The device of claim 18 further comprising a hard mask on a surface of the top electrode, the hard mask adjacent to an inner sidewall of the spacer, wherein the hard mask comprises tantalum nitride.

20. The device of claim 11 , wherein:
the bottom electrode comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen;
the dielectric layer comprises hafnium oxide; and
the top electrode comprises titanium nitride.

Assignees

• IBM

Inventors

• Ando Takashi
• Miyazoe Hiroyuki
• Cartier Eduard Albert
• Khan Babar
• Kim Youngseok
• Kong Dexin
• Seo Soon-Cheon
• De Souza Joel P

Classifications

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title