Resistive memory devices with a multi-component electrode

Patent metadata

Field	Value
Publication number	US-9847378-B2
Application number	US-201415306125-A
Country	US
Kind code	B2
Filing date	Apr 30, 2014
Priority date	Apr 30, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

First claim

What is claimed is:

1. A resistive memory device, comprising:
a conductor; and
a resistive memory stack positioned in contact with the conductor, the resistive memory stack including:
a multi-component electrode including:
a base electrode having a surface and an oxidized portion; and
an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands; and one of
i) a switching region in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or
ii) a switching region in contact with the conductor, with the inert material electrode, and with the oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

2. The resistive memory device as defined in claim 1 wherein the inert material electrode is in the form of the discontinuous nano-islands, and wherein the oxidized portion of the base electrode includes the surface of the base electrode between the discontinuous nano-islands.

3. The resistive memory device as defined in claim 2 wherein each of the discontinuous nano-islands has an aspect ratio (height:width) ranging from about 1:5 to about 1.1.

4. The resistive memory device as defined in claim 1 wherein the inert material electrode is in the form of the thin layer, and wherein a thickness of the thin layer is 10 nm or less.

5. The resistive memory device as defined in claim 1 wherein:
the base electrode is selected from the group consisting of titanium nitride, tantalum nitride, tungsten, aluminum, copper, and combinations thereof; and
the inert material electrode is electrically conductive and inert to oxidation and is selected from the group consisting of platinum, gold, iridium, ruthenium, metal carbide, metal boride, and combinations thereof.

6. The resistive memory device as defined in claim 1 wherein:
the conductor is an other multi-component electrode including:
a second base electrode having a second surface; and
a second inert material electrode on the second base electrode surface in a second form of i) a second thin layer, or ii) a second set of discontinuous nano-islands; and one of
i) the switching region is in contact with the second inert material electrode when the second inert material electrode is in the form of the second thin layer; or
ii) the switching region is in contact with the second inert material electrode and with a second oxidized portion of the second base electrode when the second inert material electrode is in the form of the second set of discontinuous nano-islands.

7. The resistive memory device as defined in claim 1 wherein the switching region includes:
a metal oxide layer having an oxygen-rich portion and an oxygen-deficient portion; and
a metal layer in contact with the oxygen-deficient portion and with the conductor.

8. The resistive memory device as defined in claim 1 , further comprising a second conductor crossing the conductor at a non-zero angle, wherein the base electrode of the multi-component electrode is positioned on the second conductor.

9. The resistive memory device as defined in claim 1 , further comprising an interlayer dielectric surrounding at least the switching region.

10. The resistive memory device as defined in claim 1 wherein the resistive memory device has a crossbar configuration or a non-crossbar configuration.

11. A resistive memory device, comprising:
a first conductor;
a second conductor;
a resistive memory stack positioned between the first and second conductors, the resistive memory stack including:
a multi-component electrode on the first conductor, the multi-component electrode including:
a base electrode having a surface; and
an inert material electrode on the base electrode surface in a form of discontinuous nano-islands;
wherein the base electrode surface between the discontinuous nano-islands is an oxidized portion of the base electrode; and

a switching region in contact with the second conductor, with the inert material electrode, and with the oxidized portion of the base electrode, the switching region including:
a metal oxide layer having an oxygen-rich portion and an oxygen-deficient portion; and
a metal layer in contact with the oxygen-deficient portion.

12. A method for making a resistive memory device, the method comprising:
forming a multi-component electrode by:
forming a base electrode having an oxidized portion; and
forming an inert material electrode on a surface of the base electrode in a form of i) a thin layer, or ii) discontinuous nano-islands;
forming a switching region on the multi-component electrode such that a surface of the switching region is in i) contact with the inert material electrode when the inert material electrode is in the form of the thin layer, or ii) contact with the inert material electrode and with the oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands; and
forming a conductor in electrical contact with another surface of the switching region.

13. The method as defined in claim 12 wherein the inert material electrode is in the form of the thin layer and is formed by electroplating from a solution.

14. The method as defined in claim 12 wherein the inert material electrode is in the form of the discontinuous nano-islands, and wherein prior to forming the switching region, the method further comprises forming the oxidized portion by oxidizing the surface of the base electrode between the discontinuous nano-islands using the discontinuous nano-islands as a mask.

15. The method as defined in claim 14 wherein forming the inert material electrode is accomplished by one of:
galvanic displacement of inert material nano-particles from a solution; or
non-selective deposition of an inert metal on the surface of the base electrode.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Sheng Xia
• Jeon Yoocharn
• Yang Jianhua
• Cho Hans S
• Henze Richard H

Classifications

• H01L45/1683

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• G11C2213/73

  Array where access device function, e.g. diode function, being merged with memorizing function of memory element · CPC title

• H01L45/146

  Electricity · mapped topic