Memory controller management techniques for managing data transfer for memory access operations
US-12561277-B2 · Feb 24, 2026 · US
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Andrei Valentin patents
Andrei Valentin is listed as an inventor on 97 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Andrei Valentin |
| Total patents | 97 |
| First publication | Sep 17, 2020 |
| Latest publication | Feb 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for updating memory side caches in a multi-GPU configuration
US-12561276-B2 · Feb 24, 2026 · US
Multi-tile memory management
US-12554674-B2 · Feb 17, 2026 · US
Dynamic memory reconfiguration
US-2025378045-A1 · Dec 11, 2025 · US
Dynamic memory reconfiguration
US-12386779-B2 · Aug 12, 2025 · US
Prefetch status notification for memory prefetching
US-12373912-B2 · Jul 29, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-2025209564-A1 · Jun 26, 2025 · US
On chip dense memory for temporal buffering
US-2025200697-A1 · Jun 19, 2025 · US
Graphics processor data access and sharing
US-2025173308-A1 · May 29, 2025 · US
Systems and methods for synchronization of multi-thread lanes
US-2025156222-A1 · May 15, 2025 · US
Recent patents
Latest publications not already listed above.
Data initialization techniques
US-2025156371-A1 · May 15, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-12293431-B2 · May 6, 2025 · US
Multi-tile memory management
US-2025117356-A1 · Apr 10, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-2025103548-A1 · Mar 27, 2025 · US
Systems and methods for cache optimization
US-2025103511-A1 · Mar 27, 2025 · US
Cache structure and utilization
US-2025103546-A1 · Mar 27, 2025 · US
Systolic disaggregation within a matrix accelerator architecture
US-2025103547-A1 · Mar 27, 2025 · US
On chip dense memory for temporal buffering
US-12254526-B2 · Mar 18, 2025 · US
Data initialization techniques
US-12242414-B2 · Mar 4, 2025 · US
Scalar core integration
US-2025068588-A1 · Feb 27, 2025 · US
Systems and methods for synchronization of multi-thread lanes
US-12223353-B2 · Feb 11, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-12210477-B2 · Jan 28, 2025 · US
Graphics processor data access and sharing
US-12204487-B2 · Jan 21, 2025 · US
Multi-tile memory management
US-2025004981-A1 · Jan 2, 2025 · US
Multi-tile memory management
US-12182062-B1 · Dec 31, 2024 · US
Systems and methods for cache optimization
US-12182035-B2 · Dec 31, 2024 · US
Cache structure and utilization
US-2024411717-A1 · Dec 12, 2024 · US
Compression techniques
US-2024403259-A1 · Dec 5, 2024 · US
Cache structure and utilization
US-12153541-B2 · Nov 26, 2024 · US
Systolic disaggregation within a matrix accelerator architecture
US-12141094-B2 · Nov 12, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 97 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 77 |
| G06T1/60 | 71 |
| G06F9/3802 | 61 |
| G06F12/0862 | 57 |
| G06F9/3888 | 54 |