Multi-tile graphics processing unit
US-2025390979-A1 · Dec 25, 2025 · US
This page is not indexed by search engines while we improve data quality.
Ashbaugh Ben patents
Ashbaugh Ben is listed as an inventor on 73 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ashbaugh Ben |
| Total patents | 73 |
| First publication | Nov 7, 2017 |
| Latest publication | Dec 25, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Multi-tile graphics processing unit
US-12367540-B2 · Jul 22, 2025 · US
Multi-tile graphics processing unit
US-2025200700-A1 · Jun 19, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-2025103548-A1 · Mar 27, 2025 · US
Scalar core integration
US-2025068588-A1 · Feb 27, 2025 · US
Multi-tile graphics processing unit
US-12217327-B2 · Feb 4, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-12210477-B2 · Jan 28, 2025 · US
Graphics processor operation scheduling for deterministic latency
US-2025028675-A1 · Jan 23, 2025 · US
Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration
US-2024345990-A1 · Oct 17, 2024 · US
Scalar core integration
US-12117962-B2 · Oct 15, 2024 · US
Recent patents
Latest publications not already listed above.
Multi-tile architecture for graphics operations
US-2024320184-A1 · Sep 26, 2024 · US
Graphics processor operation scheduling for deterministic latency
US-12079155-B2 · Sep 3, 2024 · US
Compression of machine learning models utilizing pseudo-labeled data training
US-12056906-B2 · Aug 6, 2024 · US
Data prefetching for graphics data processing
US-2024256456-A1 · Aug 1, 2024 · US
Multi-tile architecture for graphics operations
US-12013808-B2 · Jun 18, 2024 · US
Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration
US-11995029-B2 · May 28, 2024 · US
Ordered thread dispatch for thread teams
US-2024111590-A1 · Apr 4, 2024 · US
Compression of machine learning models utilizing pseudo-labeled data training
US-2024070926-A1 · Feb 29, 2024 · US
Scalar core integration
US-2024045830-A1 · Feb 8, 2024 · US
Data prefetching for graphics data processing
US-11892950-B2 · Feb 6, 2024 · US
Thread group scheduling for graphics processing
US-2024028404-A1 · Jan 25, 2024 · US
Dynamic assignment of down sampling intervals for data stream processing
US-11798198-B2 · Oct 24, 2023 · US
Scalar core integration
US-11762804-B2 · Sep 19, 2023 · US
Thread group scheduling for graphics processing
US-11709714-B2 · Jul 25, 2023 · US
Dynamic assignment of down sampling intervals for data stream processing
US-2023230289-A1 · Jul 20, 2023 · US
Systems and methods for improving cache efficiency and utilization
US-11620256-B2 · Apr 4, 2023 · US
Data prefetching for graphics data processing
US-2023051190-A1 · Feb 16, 2023 · US
Multi-tile graphics processing unit
US-2023051227-A1 · Feb 16, 2023 · US
Workload scheduling and distribution on a distributed graphics device
US-2023039853-A1 · Feb 9, 2023 · US
Scalar core integration
US-2023029176-A1 · Jan 26, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 73 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 57 |
| G06T1/60 | 47 |
| G06T15/005 | 28 |
| G06F2212/401 | 27 |
| G06F2212/302 | 26 |