Memory controller management techniques for managing data transfer for memory access operations
US-12561277-B2 · Feb 24, 2026 · US
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Macpherson Mike patents
Macpherson Mike is listed as an inventor on 107 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Macpherson Mike |
| Total patents | 107 |
| First publication | Nov 1, 2018 |
| Latest publication | Feb 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for updating memory side caches in a multi-GPU configuration
US-12561276-B2 · Feb 24, 2026 · US
Multi-tile memory management
US-12554674-B2 · Feb 17, 2026 · US
Systolic array having support for output sparsity
US-2026010345-A1 · Jan 8, 2026 · US
Register file for systolic array
US-2025390307-A1 · Dec 25, 2025 · US
Hardware Support for Activation Functions within a Matrix Engine
US-2025315405-A1 · Oct 9, 2025 · US
Systolic array having support for output sparsity
US-12399685-B2 · Aug 26, 2025 · US
Graphics architecture including a neural network pipeline
US-2025252650-A1 · Aug 7, 2025 · US
Prefetch status notification for memory prefetching
US-12373912-B2 · Jul 29, 2025 · US
Register file for systolic array
US-12346694-B2 · Jul 1, 2025 · US
Recent patents
Latest publications not already listed above.
Sparse optimizations for a matrix accelerator architecture
US-2025209564-A1 · Jun 26, 2025 · US
On chip dense memory for temporal buffering
US-2025200697-A1 · Jun 19, 2025 · US
Implicit fence for write messages
US-12321310-B2 · Jun 3, 2025 · US
Graphics processor data access and sharing
US-2025173308-A1 · May 29, 2025 · US
Architecture for block sparse operations on a systolic array
US-2025166114-A1 · May 22, 2025 · US
Data initialization techniques
US-2025156371-A1 · May 15, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-12293431-B2 · May 6, 2025 · US
Multi-tile memory management
US-2025117356-A1 · Apr 10, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-2025103548-A1 · Mar 27, 2025 · US
Cache structure and utilization
US-2025103546-A1 · Mar 27, 2025 · US
Architecture for block sparse operations on a systolic array
US-2025104180-A1 · Mar 27, 2025 · US
Systolic disaggregation within a matrix accelerator architecture
US-2025103547-A1 · Mar 27, 2025 · US
On chip dense memory for temporal buffering
US-12254526-B2 · Mar 18, 2025 · US
Data initialization techniques
US-12242414-B2 · Mar 4, 2025 · US
Scalar core integration
US-2025068588-A1 · Feb 27, 2025 · US
Graphics architecture including a neural network pipeline
US-12229867-B2 · Feb 18, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-12210477-B2 · Jan 28, 2025 · US
Graphics processor operation scheduling for deterministic latency
US-2025028675-A1 · Jan 23, 2025 · US
Graphics processor data access and sharing
US-12204487-B2 · Jan 21, 2025 · US
Architecture for block sparse operations on a systolic array
US-12198222-B2 · Jan 14, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 107 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 87 |
| G06N3/0464 | 77 |
| G06N3/08 | 72 |
| G06T1/60 | 70 |
| G06F12/0862 | 67 |