Broadcast asynchronous loads to shared local memory
US-12585590-B2 · Mar 24, 2026 · US
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Ranganathan Vasanth patents
Ranganathan Vasanth is listed as an inventor on 383 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ranganathan Vasanth |
| Total patents | 383 |
| First publication | Mar 24, 2016 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Graphics processor register file including a low energy portion and a high capacity portion
US-12579072-B2 · Mar 17, 2026 · US
Flexible partitioning of GPU resources
US-12572392-B2 · Mar 10, 2026 · US
Graphics processing unit processing and caching improvements
US-12572997-B2 · Mar 10, 2026 · US
Systems and methods for updating memory side caches in a multi-GPU configuration
US-12561276-B2 · Feb 24, 2026 · US
Multi-tile memory management
US-12554674-B2 · Feb 17, 2026 · US
Post-synchronization operations in multi-tile processor computing
US-2026037477-A1 · Feb 5, 2026 · US
Apparatus and method for throttling a ray tracing pipeline
US-12541908-B2 · Feb 3, 2026 · US
Load store bank aware thread scheduling techniques
US-12504989-B2 · Dec 23, 2025 · US
Multi-render partitioning
US-12499503-B2 · Dec 16, 2025 · US
Recent patents
Latest publications not already listed above.
Dynamic memory reconfiguration
US-2025378045-A1 · Dec 11, 2025 · US
Graphics processing unit processing and caching improvements
US-12493922-B2 · Dec 9, 2025 · US
Systolic arithmetic on sparse data
US-2025363674-A1 · Nov 27, 2025 · US
Apparatus and method for thread dispatch throttle control
US-2025355670-A1 · Nov 20, 2025 · US
Quantum-based dispatch of workgroups
US-2025342384-A1 · Nov 6, 2025 · US
Coordination and increased utilization of graphics processors during inference
US-12462328-B2 · Nov 4, 2025 · US
Dynamic precision for neural network compute operations
US-2025299032-A1 · Sep 25, 2025 · US
Gpu asynchronous matrix multiply accumulate applications
US-2025291590-A1 · Sep 18, 2025 · US
Graphics processor addressable barriers
US-2025291756-A1 · Sep 18, 2025 · US
Systolic array matrix accelerator for graphics processing unit applications
US-2025292354-A1 · Sep 18, 2025 · US
Efficient data sharing for graphics data processing operations
US-2025291744-A1 · Sep 18, 2025 · US
Providing native support for generic pointers in a graphics processing unit
US-2025272777-A1 · Aug 28, 2025 · US
Allocation and synchronization of multiple queues by a graphics processing unit
US-2025265762-A1 · Aug 21, 2025 · US
Dynamic memory reconfiguration
US-12386779-B2 · Aug 12, 2025 · US
Generation and storage of compressed z-planes in graphics processing
US-2025232397-A1 · Jul 17, 2025 · US
Graphics processor mid-thread preemption
US-2025232511-A1 · Jul 17, 2025 · US
Bindless thread dispatch mid-thread preemption on a graphics processor
US-2025231769-A1 · Jul 17, 2025 · US
Systolic arithmetic on sparse data
US-12361600-B2 · Jul 15, 2025 · US
Dynamic precision for neural network compute operations
US-12346798-B2 · Jul 1, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-2025209564-A1 · Jun 26, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 383 |
| Intel Corpoartion | 1 |
| Intel Coroporation | 1 |
| Intel Corpoation | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 267 |
| G06T1/60 | 203 |
| G06N3/0464 | 138 |
| G06F9/3888 | 126 |
| G06N3/0442 | 122 |