Spin-orbit torque MRAM structure and manufacture thereof

Patent metadata

Field	Value
Publication number	US-12201030-B2
Application number	US-202318231414-A
Country	US
Kind code	B2
Filing date	Aug 8, 2023
Priority date	May 11, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
depositing a film stack on a bottom electrode, the bottom electrode having a gap formed therein and separating a first conductive structure and a second conductive structure of the bottom electrode, the film stack deposited over the gap and overlapping at least a portion of each of the first and second conductive structures, the film stack comprising a spin-orbit torque (SOT) layer, a free layer, a tunneling barrier layer, and a reference layer;
patterning the film stack such that sidewalls of the free layer, the tunneling barrier layer, and the reference layer are substantially aligned with a sidewall of the SOT layer, wherein the film stack remains overlapping with the gap and at least a portion of each of the first and second conductive structures;
forming a top electrode over the film stack;
depositing an encapsulation layer over sidewalls of the free layer, the tunneling barrier layer, the reference layer, and the SOT layer, the encapsulation layer comprising silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ); and
depositing a dielectric fill layer over the encapsulation layer, the dielectric fill layer having a top surface coplanar with a top surface of the film stack.

2. The method of claim 1 , wherein the free layer, tunneling barrier layer, the reference layer, and the SOT layer are patterned during a single etching process.

3. The method of claim 2 , wherein the free layer, the tunneling barrier layer, the reference layer, and the SOT layer share a common dimension after patterning.

Assignees

• Applied Materials Inc

Inventors

• Yu Minrui
• Wang Wenhui
• Ahn Jaesoo
• Kim Jong Mun
• Patel Sahil
• Xue Lin
• Park Chando
• Pakala Mahendra
• Ying Chentsau Chris
• Dai Huixiong
• Ngai Christopher S

Classifications

• H10N52/80

  Constructional details · CPC title

• H10N52/01

  Manufacture or treatment · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• G01R33/095

  extraordinary magnetoresistance sensors · CPC title