Semiconductor device having dummy structures in a peripheral region and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12185548-B2
Application number	US-202117318306-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Sep 25, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a peripheral circuit region including a first substrate and a plurality of circuit elements on the first substrate; and
at least one memory cell region on the peripheral circuit region,
wherein the at least one memory cell region includes:
a second substrate on the peripheral circuit region;
a memory stack structure including a first stack structure and a second stack structure, the first stack structure including a plurality of first gate electrodes and a plurality of first interlayer insulating layers alternately stacked over the second substrate, and the second stack structure including a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternately stacked above the first stack structure, so as to be farther away from the second substrate than the first stack structure in a vertical direction;
a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate, the plurality of channel structures each including a respective channel layer;
at least one first dummy structure over the second substrate, the at least one first dummy structure spaced apart from at least one side of the first stack structure, and the at least one first dummy structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked;
at least one second dummy structure over the at least one first dummy structure, so as to be farther away from e second substrate than the first dummy structure in the vertical direction, the at least one second dummy structure spaced apart from at least one side of the second stack structure, the at least one second dummy structure including a plurality of third insulating layers and a plurality of fourth insulating layers alternately stacked;
at least a portion of the at least one first dummy structure does not overlap the at least one second dummy structure in the vertical direction; and wherein

the plurality of second insulating layers are located at height levels corresponding to height levels of the plurality of first gate electrodes, respectively,
the plurality of second insulating layers are formed of a material different from a material of the plurality of first gate electrodes,
the plurality of fourth insulating layers are located at height levels corresponding to height levels of the plurality of second gate electrodes, respectively,
the plurality of fourth insulating layers are formed of a material different from a material of the plurality of second gate electrodes, and
wherein the second dummy structure shares no surface with the first stack structure and the second stack structure.

2. The semiconductor device of claim 1 , wherein an uppermost second insulating layer among the plurality of second insulating layers of the at least one first dummy structure does not overlap the at least one second dummy structure in the vertical direction.

3. The semiconductor device of claim 1 , wherein at least a portion of a surface of at least one side of the at least one first dummy structure does not overlap the at least one second dummy structure in the vertical direction.

4. The semiconductor device of claim 1 , wherein the at least one first dummy structure and the at least one second dummy structure include a plurality of steps having a staircase shape, and
wherein an uppermost step of the plurality of steps of the at least one first dummy structure does not overlap a lowermost step of the plurality of steps of the at least one second dummy structure in the vertical direction.

5. The semiconductor device of claim 4 , wherein a lowermost step of the plurality of steps of the at least one first dummy structure does not overlap the lowermost step of the plurality of steps of the at least one second dummy structure in the vertical direction.

6. The semiconductor device of claim 1 , wherein side surfaces of the at least one first dummy structure and the at least one second dummy structure are inclined with respect to an upper surface of the second substrate.

7. The semiconductor device of claim 1 , further comprising:
a plurality of through-contact plugs penetrating through the second substrate and at least one of the at least one first dummy structure and the at least one second dummy structure, and the plurality of through-contact plugs are electrically connected to the plurality of circuit elements of the peripheral circuit region; and
a guard ring structure adjacent to an edge region of the semiconductor device, the guard ring structure surrounding the first and second stack structures and the at least one first dummy structure and the at least one second dummy structure, the guard ring structure penetrating through first and second capping insulating layers, and the guard ring structure connected to the first substrate.

8. The semiconductor device of claim 1 , wherein the at least one first dummy structure is a plurality of first dummy structures, and
wherein the at least one second dummy structure is a plurality of second dummy structures.

9. The semiconductor device of claim 8 , wherein a number of the plurality of second dummy structures is greater than a number of the plurality of first dummy structures.

10. The semiconductor device of claim 8 , wherein a number of the plurality of first dummy structures is greater than a number of the plurality of second dummy structures.

11. A semiconductor device comprising:
a peripheral circuit region including a first substrate and a plurality of circuit elements provided on the first substrate;
a second substrate on the peripheral circuit region;
a memory cell structure on the second substrate; and
a dummy structure on at least one side of the memory cell structure, the dummy structure on the second substrate,
wherein the memory cell structure includes:
a first stack structure including a plurality of first gate electrodes and a plurality of first interlayer insulating layers alternately stacked over the second substrate;
a second stack structure including a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternately stacked above the first stack structure, so as to be farther away from the second substrate than the first stack structure in a vertical direction; and
a plurality of channel structures penetrating through the first stack structure and the second stack structure, the plurality of channel structures connected to the second substrate, and

wherein the dummy structure includes:
a first dummy structure over the second substrate, the first dummy structure spaced apart from the first stack structure, and the first dummy structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked; and
a second dummy structure over the second substrate, so as to be farther way from the second substrate than the first dummy structure in the vertical direction, the second dummy structure spaced apart from the second stack structure and the first dummy structure, the second dummy structure including a plurality of third insulating layers and a plurality of fourth insulating layers alternately stacked,

wherein a central axis between side surfaces of the second dummy structure is shifted from a central axis between side surfaces of the first dummy structure in at least one direction parallel to an upper surface of the second substrate, and wherein
the plurality of second insulating layers are located at height levels corresponding to height levels of the plurality of first gate electrodes, respectively,
the plura

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Giyong
• Sim Jaeryong
• Jung Kwangyoung
• Han Jeehoon

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/50 Primary

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title