Source/drain extension regions and air spacers for nanosheet field-effect transistor structures

Patent metadata

Field	Value
Publication number	US-2020286992-A1
Application number	US-201916291443-A
Country	US
Kind code	A1
Filing date	Mar 4, 2019
Priority date	Mar 4, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, comprising:
forming a nanosheet stack over a substrate, the nanosheet stack comprising alternating sacrificial layers and channel layers, the channel layers providing nanosheet channels for one or more nanosheet field-effect transistors; forming one or more vertical fins in the nanosheet stack and at least a portion of the substrate; forming indents in sidewalls of the sacrificial layers at vertical sidewalls of the one or more vertical fins; forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the sacrificial layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins; and forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

2 . The method of claim 1 , wherein forming the nanosheet stack comprises forming the channel layers with a first thickness and forming the sacrificial layers with a second thickness less than the first thickness.

3 . The method of claim 2 , wherein the channel layers comprise silicon and the sacrificial layers comprise silicon germanium.

4 . The method of claim 3 , wherein forming the nanosheet extension regions comprises performing a thermal anneal that drives in germanium from the sacrificial layers to the channel layers.

5 . The method of claim 4 , wherein the thermal anneal produces a boundary curve that gradually changes as distance from the indented sidewalls of the sacrificial layers towards the vertical sidewalls of the channel layers increases.

6 . The method of claim 4 , wherein performing the thermal anneal comprises rapid thermal processing at a temperature in the range of about 800 degrees Celsius to about 900 degrees Celsius for a duration of approximately ten minutes.

7 . The method of claim 1 , wherein forming the inner spacers comprises depositing spacer material utilizing atomic layer deposition to pinch off the spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers leaving at least a portion of space defined by the indented sidewalls as the air gaps.

8 . The method of claim 1 , further comprising, prior to formation of the indented sidewalls of the sacrificial layers:
forming an isolation layer over at least a portion of a top surface of nanosheet stacks; forming a dummy gate over a top surface of the isolation layer; and forming sidewall spacers over a remaining portion of the top surface of the nanosheet stacks surrounding the isolation layer and the dummy gate.

9 . The method of claim 8 , further comprising, subsequent to formation of the inner spacers and air gaps, performing a replacement metal gate process to replace the dummy gate and remaining portions of the sacrificial layers with a gate stack.

10 . The method of claim 9 , further comprising forming source/drain regions over portions of a top surface of the substrate surrounding the sidewalls of the one or more vertical fins and the nanosheet stack.

11 . The method of claim 10 , wherein outer edges of the nanosheet extension regions provide a starting surface for epitaxial growth of the source/drain regions.

12 . The method of claim 1 , wherein forming the indents in the sidewalls of the sacrificial layers comprises:
forming first indents in the sidewalls of the sacrificial layers prior to forming the nanosheet extension regions; and forming second indents in the sidewalls of the sacrificial layers subsequent to forming the nanosheet extension regions; wherein the air gaps are formed in at least a portion of the space defined by the second indents.

13 . A semiconductor structure, comprising:
a substrate; one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors; the gate stack layers having indented sidewalls; the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins; inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins; and air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

14 . The semiconductor structure of claim 13 , further comprising:
an isolation layer disposed over at least a portion of a top surface of the nanosheet stack; a gate stack disposed over a top surface of the isolation layer; and sidewall spacers disposed over a remaining portion of the top surface of the nanosheet stack surrounding the isolation layer and the gate stack.

15 . The semiconductor structure of claim 13 , further comprising source/drain regions disposed over portions of the top surface of the substrate surrounding the sidewalls of the one or more vertical fins.

16 . The semiconductor structure of claim 15 , wherein the nanosheet extension regions have a curved thickness profile that increases from the first thickness to the second thickness from the indented sidewalls of the gate stack layers to the source/drain regions.

17 . An integrated circuit comprising:
a nanosheet field-effect transistor structure comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
the gate stack layers having indented sidewalls;
the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins; and
air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

18 . The integrated circuit of claim 17 , wherein the nanosheet field-ef

Assignees

• IBM

Inventors

• Song Yi
• Bi Zhenxing
• Cheng Kangguo
• Liu Chi-Chun

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title