Self-aligned inner-spacer replacement process using implantation

Patent metadata

Field	Value
Publication number	US-9831324-B1
Application number	US-201615235357-A
Country	US
Kind code	B1
Filing date	Aug 12, 2016
Priority date	Aug 12, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of silicon germanium and silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer;
forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region;
performing a germanium implantation on exposed portions of the stacked configuration in a source/drain region, wherein the germanium implantation increases a germanium concentration of the exposed portions of the stacked configuration; and
selectively removing silicon germanium layers having increased germanium concentration from the source/drain region, wherein the removed silicon germanium layers correspond in position to the silicon germanium layers in the channel region.

2. The method according to claim 1 , wherein the selective removal stops at the silicon germanium layers in the channel region.

3. The method according to claim 1 , wherein the selective removal comprises a lateral wet etch process.

4. The method according to claim 3 , wherein the selective removal is performed using an etchant comprising a NH 4 OH:H 2 O 2 solution.

5. The method according to claim 1 , further comprising forming a spacer layer in each of openings left after selectively removing the silicon germanium layers from the source/drain region.

6. The method according to claim 1 , wherein the germanium implantation increases the germanium concentration of the exposed portions of the stacked configuration by 5% or more than 5%.

7. The method according to claim 1 , wherein the germanium implantation is performed using a plurality of implantation steps.

8. The method according to claim 7 , wherein each step of the plurality of implantation steps is performed at a different energy level.

9. The method according to claim 1 , wherein the germanium implantation is performed at a temperature greater than about 400° C.

10. The method according to claim 1 , further comprising forming a spacer layer on each of the plurality of dummy gates, and on the exposed portions of the stacked configuration.

11. The method according to claim 1 , further comprising laterally recessing the germanium implanted exposed portions of the stacked configuration in the source/drain region.

Assignees

• IBM

Inventors

• Chao Robin Hsin-Kuo
• Guillorn Michael A
• Liu Chi-Chun
• Mochizuki Shogo
• Yeung Chun W

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H01L29/66553

  Electricity · mapped topic