Stacked field effect transistor with wrap-around contacts

Patent metadata

Field	Value
Publication number	US-11201153-B2
Application number	US-202016801904-A
Country	US
Kind code	B2
Filing date	Feb 26, 2020
Priority date	Feb 26, 2020
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a first nanosheet stack over a substrate, the first nanosheet stack comprising a first nanosheet and a first sacrificial sheet;
forming a sacrificial spacer layer on the first nanosheet stack;
forming a second nanosheet stack on the sacrificial spacer layer, the second nanosheet stack comprising a second nanosheet and a second sacrificial sheet;
removing the sacrificial spacer layer selective to the first sacrificial sheet and the second sacrificial sheet to define a cavity between the first nanosheet stack and the second nanosheet stack;
forming a first sacrificial layer over a source or drain (S/D) region of the first nanosheet;
forming a second sacrificial layer over a S/D region of the second nanosheet;
forming a conductive gate over channel regions of the first nanosheet and the second nanosheet;
replacing the first sacrificial layer with a first wrap-around contact; and
replacing the second sacrificial layer with a second wrap-around contact.

2. The method of claim 1 further comprising:
forming the S/D region of the first nanosheet on an exposed sidewall of the first nanosheet; and
forming the S/D region of the second nanosheet on an exposed sidewall of the second nanosheet.

3. The method of claim 1 , wherein the conductive gate is formed in a replacement metal gate (RMG) process.

4. The method of claim 3 further comprising removing the first sacrificial layer and the second sacrificial layer after the RMG process.

5. The method of claim 4 further comprising patterning the first sacrificial layer and the second sacrificial layer to provide a horizontal offset between the first sacrificial layer and the second sacrificial layer.

6. The method of claim 5 , wherein
removing the first sacrificial layer comprises: forming a first trench that exposes a surface of the first sacrificial layer; and
removing the second sacrificial layer comprises forming a second trench that exposes a surface of the second sacrificial layer.

7. The method of claim 1 , wherein the S/D region of the first nanosheet comprises a p-type epitaxy and the S/D region of the second nanosheet comprises an n-type epitaxy.

8. The method of claim 1 further comprising filling the cavity with a dielectric material.

9. A method for forming a semiconductor device, the method comprising:
forming a p-type nanosheet stack over a substrate, the p-type nanosheet stack comprising a first nanosheet and a second nanosheet;
forming an n-type nanosheet stack over the p-type nanosheet stack, the n-type nanosheet stack comprising a third nanosheet and a fourth nanosheet;
forming a first sacrificial layer over a first source or drain (S/D) region of the p-type nanosheet stack;
forming an isolation dielectric on the first sacrificial layer;
forming a second sacrificial layer over a second S/D region of the n-type nanosheet stack, the second sacrificial layer on the isolation dielectric; and
replacing the first sacrificial layer with a first wrap-around contact and the second sacrificial layer with a second wrap-around contact.

10. The method of claim 9 further comprising forming a dielectric spacer between the p-type nanosheet stack and the n-type nanosheet stack.

11. The method of claim 9 further comprising forming the S/D region of the first nanosheet on an exposed sidewall of the first nanosheet and forming the S/D region of the second nanosheet on an exposed sidewall of the second nanosheet.

12. The method of claim 9 further comprising forming a conductive gate using a replacement metal gate (RMG) process.

13. The method of claim 12 further comprising removing the first sacrificial layer and the second sacrificial layer after the RMG process.

14. The method of claim 13 further comprising patterning the first sacrificial layer and the second sacrificial layer to provide a horizontal offset between the first sacrificial layer and the second sacrificial layer.

15. The method of claim 14 , wherein removing the first sacrificial layer comprises forming a first trench that exposes a surface of the first sacrificial layer and removing the second sacrificial layer comprises forming a second trench that exposes a surface of the second sacrificial layer.

Assignees

• IBM

Inventors

• Xie Ruilong
• Yeh Chun-Chen
• Reznicek Alexander
• Guo Dechao

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title