Semiconductor package with metal posts from structured leadframe

Patent metadata

Field	Value
Publication number	US-12176222-B2
Application number	US-202117536538-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Nov 29, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

First claim

What is claimed is:

1. A method of forming a semiconductor package, the method comprising:
providing a metal baseplate comprising a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section;
mounting a semiconductor die on the upper surface of the metal baseplate;
forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section;
electrically connecting terminals of the semiconductor die to the metal posts; and
removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body,
wherein the semiconductor die is mounted with at least some of the terminals facing away from the metal baseplate, and wherein electrically connecting terminals of the semiconductor die to the metal posts comprises:
providing conductive pillars on the terminals of the semiconductor die that face away from the metal baseplate before forming the encapsulant body;
exposing upper ends of the conductive pillars at a second surface of the encapsulant body after forming the encapsulant body; and
forming conductive tracks in the second surface of the encapsulant body.

2. The method of claim 1 , wherein the package contacts comprise ends of the metal posts that are exposed at one or both of the first surface of the encapsulant body and a second surface of the encapsulant body, the second surface being opposite from the first surface.

3. The method of claim 1 , wherein removing the base section comprises one or more of: chemical etching, mechanical grinding, milling, or lasering.

4. The method of claim 1 , further comprising covering the conductive tracks with a solder resist material.

5. The method of claim 1 , wherein the electrically insulating mold compound comprises a laser-activatable mold compound, and wherein the forming conductive tracks comprises:
applying a laser to the second surface of the encapsulant body thereby forming laser activated traces in the second surface of the encapsulant body; and
performing a plating process that selectively forms the conductive tracks in the laser activated traces.

6. The method of claim 5 , wherein performing the plating process comprises:
performing an electroless plating process that forms seed layer parts of the conductive tracks; and
performing an electroplating process that forms thicker metal layer parts of the conductive tracks on top of the seed layer parts, the thicker metal layer parts being thicker than the seed layer parts; and
wherein the base section of the metal baseplate remains intact during the electroplating process.

7. The method of claim 1 , wherein the forming conductive tracks comprises:
laser assisted metal deposition; and
ink jet metal printing.

8. The method of claim 1 , further comprising:
providing a first pad in a first area of the upper surface of the base section;
providing a second pad in a second area of the upper surface of the base section, the second pad comprising metal;
mounting the semiconductor die on the first pad; and
mounting a second semiconductor die on the second pad,
wherein after removing the base section the metal pad is exposed from the first surface of the encapsulant body and forms a thermal conduction path between an outer surface of the semiconductor package and the second semiconductor die.

9. The method of claim 8 , wherein the first pad is an electrically insulating structure.

10. The method of claim 8 , wherein the first pad is an electrically conductive structure.

11. The method of claim 8 , wherein the semiconductor die is a logic device, wherein the second semiconductor die is a power switching device, and wherein the method further comprises electrically connecting a terminal of the semiconductor die to a terminal of the second semiconductor die.

12. The method of claim 1 , wherein the metal baseplate is provided to comprise a metal trace on the upper surface of the base section, and wherein the metal trace contacts the metal posts.

13. The method of claim 12 , wherein the metal baseplate is provided to comprise a die attach area on the upper surface of the metal baseplate, wherein the at least one metal trace extends between the die attach area and the metal posts, and wherein the semiconductor die is mounted on the die attach area such that one of the terminals of the semiconductor die faces and electrically connects with the metal trace.

14. The method of claim 12 , wherein the metal trace is connected between a first one of the metal posts and a second one of the metal posts, wherein electrically connecting terminals of the semiconductor die to the metal posts comprises forming a conductive track in a second surface of the encapsulant body that is opposite from the first surface of the encapsulant body, and wherein the conductive track electrically connects one of the terminals of the semiconductor die to the first one of the metal posts.

15. The method of claim 1 , further comprising forming a lead tip inspection feature of the semiconductor package, wherein forming the lead tip inspection feature comprises structuring the encapsulant body to form an exposed sidewall of one of the metal posts, and wherein the exposed sidewall extends completely between the first surface of the encapsulant body and a second surface of the encapsulant body that is opposite from the first surface.

16. The method of claim 15 , wherein forming the lead tip inspection feature further comprises structuring the encapsulant body to form a second exposed sidewall of the one of the metal posts, wherein the second exposed sidewall extends completely between the first and second surfaces of the encapsulant body, and wherein the first and second exposed sidewalls form an angled intersection with one another.

17. The method of claim 1 , further comprising:
providing a first pad that is electrically conductive on the upper surface of the base section, the first pad comprising a main pad portion and connectors that extend between the metal pad portion and at least one of the metal posts; and
mounting the semiconductor die on the main pad portion such that at least one of the terminals of the semiconductor die faces and is electrically connected to the main pad portion.

18. The method of claim 1 , wherein electrically connecting terminals of the semiconductor die to the metal posts comprises a metal structuring process that is performed after forming the encapsulant body.

19. The method of claim 1 , wherein the encapsulant body of electrically insulating mold compound is formed on the upper surface of the base section after mounting the semiconductor die on the upper surface of the metal baseplate and at least partly encapsulates the metal posts.

20. A method of forming a semiconductor package, the method comprising:
providing a metal baseplate comprising a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section;
mounting a semiconductor die on the upper surface of the metal baseplate;
forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section;
electrically connecting terminals of the semiconductor die to the metal posts;
removing the base section so as to form package contacts from the metal

Assignees

• Infineon Technologies Ag

Inventors

• Chiang Chau Fatt
• Meyer Thorsten
• Cha Chan Lam
• Daryl Wee Wern Ken
• Lee Chee Hong
• Lee Swee Kah
• Morban Norliza
• Saw Khay Chwan Andrew

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title