High-throughput additively manufactured power delivery vias and traces

Patent metadata

Field	Value
Publication number	US-12170244-B2
Application number	US-202016914062-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

First claim

We claim:

1. An integrated circuit (IC) die package substrate comprising:
a first trace upon, or embedded within, a dielectric material, wherein the first trace comprises a first metal;
a first via coupled to the first trace, wherein the first via comprises the first metal;
a second trace upon, or embedded within, the dielectric material; and
a second via coupled to the second trace, wherein at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal, wherein the second metal has a greater void % area than the first metal and wherein the second metal has a void % area of at least 0.1%.

2. The IC die package substrate of claim 1 , wherein:
the first trace has a first thickness;
the first via has a first diameter; and
at least a first portion of the second trace has a second thickness, greater than the first thickness, or the second via has a second diameter greater than the first diameter.

3. The IC die package substrate of claim 2 , wherein the first metal and the second metal both comprise predominantly Cu, and the second metal has a void % area of at least 0.5%.

4. The IC die package substrate of claim 2 , wherein the first portion of the second trace comprises a stack of both the first thickness of the first metal and a third thickness of the second metal.

5. The IC die package substrate of claim 4 , wherein:
the first trace is over a second portion of the second trace lacking the second metal; and
the second metal is laterally adjacent to the first trace.

6. The IC die package substrate of claim 5 , wherein the first trace is non-parallel to the second trace, the second portion of the second trace has only the first thickness of the first metal, and wherein:
the second trace has a first length, the first portion has a second length and the second portion has a third length, larger than a width of the first trace.

7. The IC die package substrate of claim 2 , wherein:
the first trace is within a lower-level conductor plane embedded within the dielectric material;
the first trace is coupled by the first via to a first one of a first plurality of interconnect features arrayed within an upper-level conductor plane;
the second trace is within an upper-level conductor plane, and at least a portion of the second trace has the second thickness; and
the second trace extends between a second one of the first plurality of interconnect features and a first one of a second plurality of interconnect features within the upper-level conductor plane.

8. The IC die package substrate of claim 2 , wherein the second via has the second diameter, which exceeds 100 microns in width and depth, and comprises the second metal.

9. The IC die package substrate of claim 8 , wherein:
the first trace is within a first lower-level conductor plane embedded within the dielectric material;
the first via is between the first trace and a second trace within a second lower-level conductor plane, below the first lower-level conductor plane; and
the second via extends from an upper-level conductor plane, over the first lower-level conductor plane, to the second lower-level conductor plane.

10. The IC die package substrate of claim 9 , further comprising:
a third via comprising the second metal, wherein the third via extends from the upper-level conductor plane, to a third lower-level conductor plane, below the second lower-level conductor plane.

11. The IC die package substrate of claim 8 , wherein the second via extends from a surface on a first side of the substrate to either a lower-level conductor plane or to a discrete metal slug embedded within the substrate.

12. The IC die package substrate of claim 11 , wherein the second metal comprises a concave surface recess to receive an interconnect pin of a host component within the recess.

13. The IC die package substrate of claim 12 , wherein:
the second via further comprises a surface finish within the recess and in contact with the second metal; and
the surface finish comprises a third metal having a lower bulk modulus than the second metal.

14. An electronic device comprising:
an integrated circuit (IC) die package substrate comprising:
a first trace upon, or embedded within, a dielectric material, wherein the first trace comprises a first metal;
a first via coupled to the first trace, wherein the first via comprises the first metal;
a second trace upon, or embedded within, the dielectric material; and
a second via coupled to the second trace, wherein at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal and a greater void % area than the first metal, wherein the second metal has a void % area of at least 0.5%;

a first IC die interconnected to a first side of the package substrate, wherein:
the first IC die has a signal I/O plane electrically coupled to the first trace; and
the first IC die has a power plane electrically coupled to the second trace.

15. The electronic device of claim 14 , further comprising a second IC die interconnected to the first side of the package substrate, and wherein the second trace electrically couples together a power plane of each of the first and second IC dies.

16. The electronic device of claim 15 , wherein:
the first IC die comprises a voltage regulation circuitry;
the second IC die comprises microprocessor circuitry; and
the second trace is to convey power output from the voltage regulation circuitry to the power plane of the microprocessor circuitry.

17. The electronic device of claim 14 , further comprising a printed circuit board (PCB) interconnected to a second side of the package substrate, wherein the second via comprises the second metal having a width and a depth exceeding 100 microns, and wherein a socket pin of the PCB is embedded within a recess of the second metal.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel
• Eid Feras
• Dogiamis Georgios
• Braunisch Henning
• Choi Beomseok
• Lambert William J
• Morein Stephen
• Abou-Alfotouh Ahmed
• Swan Johanna

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title