Hybrid ball grid array package for high speed interconnects

Patent metadata

Field	Value
Publication number	US-11527463-B2
Application number	US-202016984173-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	May 27, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate;
a substrate raiser positioned on the substrate, the substrate raiser having one or more conductive via;
a first solder ball coupled to the conductive via; and
one or more second solder balls positioned on the substrate, the second solder ball having a size greater than a size of the first solder ball, wherein the first solder ball and the second solder ball extend approximately a same height above the substrate;
further comprising the first solder ball and the second solder balls being attached to a printed circuit board,
wherein the substrate raiser further comprises:
a step section having a smaller conductive via; and
a semiconductor device coupled to the smaller conductive via.

2. The semiconductor package of claim 1 , wherein the first solder ball further comprises a plurality of first solder balls;
wherein the one or more second solder ball further comprises a plurality of second solder balls; and
wherein the one or more conductive via further comprises a plurality of conductive vias.

3. The semiconductor package of claim 1 , wherein a height of the semiconductor device coupled to the smaller conductive via is less than a height of the first solder ball coupled with the conductive via.

4. The semiconductor package of claim 1 , wherein a height of the semiconductor device coupled to the smaller conductive via is less than a combined height of a height of the first solder ball coupled with the conductive via together and a height for a recess provided in the printed circuit board.

5. The semiconductor package of claim 1 , wherein the semiconductor device is a passive device.

6. The semiconductor package of claim 1 , further comprising at least one die positioned over the substrate and having a vertical footprint, wherein the step section of the substrate raiser is positioned inside of the vertical footprint of the die.

7. The semiconductor package of claim 6 , wherein the at least one die further comprises two or more dies.

8. The semiconductor package of claim 6 , wherein the substrate raiser forms at least a partial perimeter outside the vertical footprint of the die.

9. The semiconductor package of claim 1 , wherein the substrate further comprises a cored substrate or a coreless substrate.

10. A method for forming a semiconductor package comprising:
forming a substrate;
forming a raiser section on the substrate;
forming at least one conductive via in the raiser section;
forming a first solder ball coupled to the at least one conductive via; and
forming a plurality of second solder balls positioned on the substrate, the second solder ball having a size greater than a size of the first solder ball, wherein the first solder ball and the second solder ball extend approximately a same height above the substrate for attachment with a printed circuit board;
further comprising attaching the first solder ball and the second solder balls to a printed circuit board;
wherein the substrate raiser further comprises a step section having a smaller conductive via; and a semiconductor device coupled to the smaller conductive via.

11. The method for forming a semiconductor package of claim 10 , further comprising:
forming a step section in the raiser section and at least one smaller conductive via in the step section by removing a portion of the raiser section by a laser or mechanical removal process; and
coupling a semiconductor device to the at least one smaller conductive via in the step section, wherein the portion removed from the raiser section forms a height for the semiconductor device coupled to the at least one smaller conductive via that is less than either a height for the first solder ball and the at least one conductive via coupled together or a combined height of the height for the first solder ball and the at least one conductive via coupled together and a height for a recess provided in the printed circuit board.

12. The method for forming a semiconductor package of claim 10 , wherein forming the raiser section on the substrate further comprises:
forming a polymer layer on the substrate by an injection molding or compression molding process; and
patterning the polymer layer to form at least a partial perimeter around a projected vertical footprint for a die to be placed on the substrate.

13. The method for forming a semiconductor package of claim 10 , wherein forming at least one conductive via in the raiser section further comprises:
forming a via opening using laser or mechanical drilling process and filling the via openings with a conductive material by an electroless or electrolytic deposition process.

14. A computing device comprising:
a circuit board;
a semiconductor package coupled with the circuit board, the semiconductor package comprising:
a substrate having top and bottom surfaces;
one or more die positioned on the top surface of the substrate;
a substrate raiser positioned on the bottom side of the substrate, the substrate raiser having at least one conductive via;
a first solder ball positioned on the at least one conductive via; and
a plurality of second solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, the second solder ball having a size greater than a size of the first solder ball, wherein the first solder ball and the second solder ball extend approximately a same distance from the substrate for attachment with the circuit board.

15. The computing device of claim 14 , wherein the first solder ball and the conductive via carries electrical signals of greater than 40 GHz and the second solder ball carries electrical signals of less than 40 GHz.

16. The computing device of claim 14 , wherein the substrate raiser further comprises:
a step section having at least one smaller conductive via; and
a semiconductor device coupled to the at least one smaller conductive via, wherein a height of the semiconductor device coupled to the at least one smaller conductive via is less than the first solder ball and the at least one conductive via.

17. The computing device of claim 16 , further comprising signal routing lines placed under the step section.

18. The computing device of claim 16 , wherein the semiconductor device is a passive device.

Assignees

• Intel Corp

Inventors

• Cheah Bok Eng
• Ong Jenny Shio Yin
• Lim Seok Ling
• Ooi Kooi Chi
• Kong Jackson Chung Peng

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/092

  Adapting interconnections, e.g. making engineering charges, repairing · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title