Multiplier circuit

Patent metadata

Field	Value
Publication number	US-12169701-B2
Application number	US-202318242603-A
Country	US
Kind code	B2
Filing date	Sep 6, 2023
Priority date	Nov 17, 2017
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

A multiplier circuit includes a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor. It further includes a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor.

First claim

The invention claimed is:

1. A multiplier circuit comprising:
a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor; and
a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor,
wherein a gate of the first transistor is electrically connected to one electrode of the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the other electrode of the first capacitor,
wherein a gate of the second transistor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,
wherein a gate of the third transistor is electrically connected to one electrode of the third capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the other electrode of the third capacitor,
wherein a gate of the fourth transistor is electrically connected to one electrode of the fourth capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the one electrode of the fourth capacitor, and
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.

2. The multiplier circuit according to claim 1 ,
wherein the other electrode of the first capacitor is electrically connected to the other electrode of the second capacitor, and
wherein the other electrode of the third capacitor is electrically connected to the other electrode of the fourth capacitor.

3. The multiplier circuit according to claim 1 , wherein each of the first circuit and the second circuit is a programming cell.

4. The multiplier circuit according to claim 1 , further comprising a switch between the first circuit and the second circuit,
wherein one electrode of the switch is electrically connected to the one of the source and the drain of the second transistor, and
wherein the other electrode of the switch is electrically connected to the one of the source and the drain of the fourth transistor.

5. The multiplier circuit according to claim 1 , further comprising a multiplication cell,
wherein the multiplication cell is electrically connected to the one of the source and the drain of the second transistor, and
wherein the multiplication cell is electrically connected to the one of the source and the drain of the fourth transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Kimura Hajime
• Fukutome Takahiro

Classifications

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F7/4991 Primary

  Overflow or underflow · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title