Semiconductor device

Patent metadata

Field	Value
Publication number	US-10114611-B2
Application number	US-201715849910-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Mar 10, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data. A reference memory cell is configured to generate a reference current corresponding to reference data. A first circuit is configured to generate and hold a third current corresponding to the difference between the first current and the reference current when the first current is lower than the reference current. A second circuit is configured to generate and hold a fourth current corresponding to the difference between the first current and the reference current when the first current is higher than the reference current. One of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a memory cell comprising a first transistor and a second transistor;
a reference memory cell comprising a third transistor and a fourth transistor; and
a current source circuit comprising a fifth transistor and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor through a first wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the sixth transistor through a second wiring,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein the semiconductor device is configured to perform a product-sum operation.

2. The semiconductor device according to claim 1 ,
wherein the memory cell further comprises a first capacitor,
wherein the reference memory cell further comprises a second capacitor,
wherein an electrode of the first capacitor is electrically connected to the gate of the first transistor, and
wherein an electrode of the second capacitor is electrically connected to the gate of the third transistor.

3. The semiconductor device according to claim 1 ,
wherein the memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data, and
wherein the reference memory cell is configured to generate a reference current corresponding to reference data.

4. The semiconductor device according to claim 1 , further comprising:
a first circuit configured to generate a third current; and
a second circuit configured to generate a fourth current,
wherein one of the first circuit and the second circuit is configured to generate a fifth current.

5. A semiconductor device comprising:
a memory cell comprising a first transistor and a second transistor;
a reference memory cell comprising a third transistor and a fourth transistor; and
a current source circuit comprising a fifth transistor and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor through a first wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the sixth transistor through a second wiring,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the semiconductor device is configured to perform a product-sum operation, and
wherein each of the second transistor and the fourth transistor comprises an oxide semiconductor in a channel region.

6. The semiconductor device according to claim 5 ,
wherein the memory cell further comprises a first capacitor,
wherein the reference memory cell further comprises a second capacitor,
wherein an electrode of the first capacitor is electrically connected to the gate of the first transistor, and
wherein an electrode of the second capacitor is electrically connected to the gate of the third transistor.

7. The semiconductor device according to claim 5 ,
wherein the memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data, and
wherein the reference memory cell is configured to generate a reference current corresponding to reference data.

8. The semiconductor device according to claim 5 , further comprising:
a first circuit configured to generate a third current; and
a second circuit configured to generate a fourth current,
wherein one of the first circuit and the second circuit is configured to generate a fifth current.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G06F17/00

  Digital computing or data processing equipment or methods, specially adapted for specific functions (information retrieval, database structures or file system structures therefor G06F16/00) · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title