Semiconductor device

Patent metadata

Field	Value
Publication number	US-9934826-B2
Application number	US-201715481937-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 14, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

To provide a semiconductor device including a first memory cell for holding first analog data, a second memory cell for holding reference analog data, and an offset circuit. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is supplied. The offset circuit supplies a third current corresponding to a differential current between the first current and the second current. The first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is supplied. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained. By providing a plurality of product-sum operation circuits that can be freely connected, a hierarchical neural network can be formed.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first product-sum operation circuit comprising a first terminal;
a second product-sum operation circuit comprising a second terminal;
a first switch circuit comprising a third terminal and a fourth terminal, the third terminal being electrically connected to the first terminal; and
a second switch circuit comprising a fifth terminal and a sixth terminal, the fifth terminal being electrically connected to the second terminal,
wherein the fourth terminal and the sixth terminal are electrically connected to each other,
wherein the first switch circuit is configured to control a conduction state between the third terminal and the fourth terminal, and
wherein the second switch circuit is configured to control a conduction state between the fifth terminal and the sixth terminal.

2. The semiconductor device according to claim 1 ,
wherein the first switch circuit further comprises a first transistor and a second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the third terminal, and
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth terminal.

3. The semiconductor device according to claim 2 ,
wherein the first switch circuit further comprises a capacitor,
wherein a first electrode of the capacitor is electrically connected to the one of the source and the drain of the first transistor, and
wherein a second electrode of the capacitor is electrically connected to a wiring for supplying a low-level potential.

4. The semiconductor device according to claim 2 , wherein the first transistor comprises an oxide semiconductor layer comprising indium and zinc.

5. The semiconductor device according to claim 1 , wherein the semiconductor device is configured to perform pattern recognition and associative storage.

6. A semiconductor device comprising a plurality of product-sum operation circuits arranged in a matrix, the plurality of product-sum operation circuits comprising:
a first product-sum operation circuit comprising a first terminal;
a second product-sum operation circuit comprising a second terminal;
a first switch circuit comprising a third terminal and a fourth terminal, the third terminal being electrically connected to the first terminal; and
a second switch circuit comprising a fifth terminal and a sixth terminal, the fifth terminal being electrically connected to the second terminal,
wherein the first product-sum operation circuit and the first switch circuit are arranged in a first row and a first column of the matrix, and the second product-sum operation circuit and the second switch circuit are in a second row and the first column of the matrix,
wherein the fourth terminal and the sixth terminal are electrically connected to each other,
wherein the first switch circuit is configured to control a conduction state between the third terminal and the fourth terminal, and
wherein the second switch circuit is configured to control a conduction state between the fifth terminal and the sixth terminal.

7. The semiconductor device according to claim 6 ,
wherein the first switch circuit further comprises a first transistor and a second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the third terminal, and
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth terminal.

8. The semiconductor device according to claim 7 ,
wherein the first switch circuit further comprises a capacitor,
wherein a first electrode of the capacitor is electrically connected to the one of the source and the drain of the first transistor, and
wherein a second electrode of the capacitor is electrically connected to a wiring for supplying a low-level potential.

9. The semiconductor device according to claim 7 , wherein the first transistor comprises an oxide semiconductor layer comprising indium and zinc.

10. The semiconductor device according to claim 6 , wherein the semiconductor device is configured to perform pattern recognition and associative storage.

11. A semiconductor device comprising:
a first product-sum operation circuit comprising a first terminal;
a second product-sum operation circuit comprising a second terminal;
a first switch circuit comprising a third terminal and a fourth terminal, the third terminal being electrically connected to the first terminal; and
a second switch circuit comprising a fifth terminal and a sixth terminal, the fifth terminal being electrically connected to the second terminal,
wherein the fourth terminal and the sixth terminal are electrically connected to each other,
wherein the first switch circuit is configured to control a conduction state between the third terminal and the fourth terminal,
wherein the second switch circuit is configured to control a conduction state between the fifth terminal and the sixth terminal, and
wherein each of the first product-sum operation circuit and the second product-sum operation circuit comprises a memory cell array and an offset circuit electrically connected to the memory cell array.

12. The semiconductor device according to claim 11 ,
wherein the first switch circuit further comprises a first transistor and a second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the third terminal, and
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth terminal.

13. The semiconductor device according to claim 12 ,
wherein the first switch circuit further comprises a capacitor,
wherein a first electrode of the capacitor is electrically connected to the one of the source and the drain of the first transistor, and
wherein a second electrode of the capacitor is electrically connected to a wiring for supplying a low-level potential.

14. The semiconductor device according to claim 12 , wherein the first transistor comprises an oxide semiconductor layer comprising indium and zinc.

15. The semiconductor device according to claim 11 , wherein the semiconductor device is configured to perform pattern recognition and associative storage.

16. The semiconductor device according to claim 11 , wherein the offset circuit comprises a constant current circuit and a current mirror circuit.

17. The semiconductor device according to claim 11 ,
wherein the memory cell array comprises a first memory cell and a second memory cell,
wherein the first memory cell is configured to supply a first current in accordance with a first signal,
wherein the second memory cell is configured to supply a second current in accordance with the first signal,
wherein the offset circuit is configured to supply a third current corresponding to a first differential current between the first current and the second current,
wherein the first memory cell is configured to supply a fourth current in accordance with a second signal,
wherein the second memory cell is configured to supply a fifth current in accordance with the second signal, and
wherein the first product-s

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G06N3/063

  using electronic means · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/048

  Activation functions · CPC title

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G06N3/08

  Learning methods · CPC title